Parameters |
Base Part Number |
74ABT374 |
JESD-30 Code |
R-PDSO-G20 |
Function |
Standard |
Qualification Status |
Not Qualified |
Output Type |
Tri-State, Non-Inverted |
Number of Elements |
1 |
Supply Voltage-Max (Vsup) |
5.5V |
Power Supplies |
5V |
Supply Voltage-Min (Vsup) |
4.5V |
Load Capacitance |
50pF |
Number of Ports |
2 |
Clock Frequency |
300MHz |
Family |
ABT |
Current - Quiescent (Iq) |
250μA |
Output Characteristics |
3-STATE |
Current - Output High, Low |
32mA 64mA |
Output Polarity |
TRUE |
Max I(ol) |
0.064 A |
Number of Bits per Element |
8 |
Max Propagation Delay @ V, Max CL |
4.9ns @ 5V, 50pF |
Prop. Delay@Nom-Sup |
5.2 ns |
Trigger Type |
Positive Edge |
Input Capacitance |
4pF |
Propagation Delay (tpd) |
5.2 ns |
Power Supply Current-Max (ICC) |
30mA |
Max Frequency@Nom-Sup |
200000000Hz |
Height Seated (Max) |
2.65mm |
Width |
7.5mm |
RoHS Status |
ROHS3 Compliant |
Mounting Type |
Surface Mount |
Package / Case |
20-SOIC (0.295, 7.50mm Width) |
Surface Mount |
YES |
Operating Temperature |
-40°C~85°C TA |
Packaging |
Tube |
Series |
74ABT |
JESD-609 Code |
e4 |
Part Status |
Obsolete |
Moisture Sensitivity Level (MSL) |
1 (Unlimited) |
Number of Terminations |
20 |
Type |
D-Type |
Terminal Finish |
Nickel/Palladium/Gold (Ni/Pd/Au) |
Subcategory |
FF/Latches |
Technology |
BICMOS |
Voltage - Supply |
4.5V~5.5V |
Terminal Position |
DUAL |
Terminal Form |
GULL WING |
Peak Reflow Temperature (Cel) |
260 |
Supply Voltage |
5V |
Time@Peak Reflow Temperature-Max (s) |
30 |
74ABT374AD,112 Overview
The flip flop is packaged in a case of 20-SOIC (0.295, 7.50mm Width). A package named Tubeincludes it. As configured, the output uses Tri-State, Non-Inverted. JK flip flop uses Positive Edgeas the trigger. Surface Mountmounts this electrical part. A voltage of 4.5V~5.5Vis used as the supply voltage. In this case, the operating temperature is -40°C~85°C TA. This D latch has the type D-Type. The 74ABTseries comprises this type of FPGA. It should not exceed 300MHzin its output frequency. A total of 1elements are contained within it. As a result, it consumes 250μA quiescent current. Terminations are 20. This D latch belongs to the family of 74ABT374. A voltage of 5V provides power to the D latch. JK flip flop input capacitance is 4pF farads. This D flip flop belongs to the family of ABT. There is a base part number FF/Latchesfor the RS flip flops. Vsup reaches 5.5V, the maximal supply voltage. It is imperative that the supply voltage (Vsup) is maintained above 4.5Vin order to ensure normal operation. The system runs on a power supply of 5V watts. The D flip flop is embedded with 2ports.
74ABT374AD,112 Features
Tube package
74ABT series
5V power supplies
74ABT374AD,112 Applications
There are a lot of NXP USA Inc. 74ABT374AD,112 Flip Flops applications.
- ATE
- Balanced 24 mA output drivers
- Shift registers
- Safety Clamp
- Single Down Count-Control Line
- Load Control
- Frequency Dividers
- High Performance Logic for test systems
- Memory
- ESD performance