Parameters |
Mounting Type |
Surface Mount |
Package / Case |
24-SSOP (0.209, 5.30mm Width) |
Surface Mount |
YES |
Operating Temperature |
-40°C~85°C TA |
Packaging |
Tube |
Series |
74ABT |
JESD-609 Code |
e4 |
Part Status |
Obsolete |
Moisture Sensitivity Level (MSL) |
1 (Unlimited) |
Number of Terminations |
24 |
Type |
D-Type |
Terminal Finish |
NICKEL PALLADIUM GOLD |
Additional Feature |
POWER OFF DISABLE OUTPUTS TO PERMIT LIVE INSERTION; WITH POWER-UP RESET |
Subcategory |
FF/Latches |
Technology |
BICMOS |
Voltage - Supply |
4.5V~5.5V |
Terminal Position |
DUAL |
Terminal Form |
GULL WING |
Peak Reflow Temperature (Cel) |
260 |
Supply Voltage |
5V |
Terminal Pitch |
0.65mm |
Time@Peak Reflow Temperature-Max (s) |
30 |
Base Part Number |
74ABT821 |
JESD-30 Code |
R-PDSO-G24 |
Function |
Standard |
Qualification Status |
Not Qualified |
Output Type |
Tri-State, Non-Inverted |
Number of Elements |
1 |
Supply Voltage-Max (Vsup) |
5.5V |
Power Supplies |
5V |
Supply Voltage-Min (Vsup) |
4.5V |
Load Capacitance |
50pF |
Number of Ports |
2 |
Clock Frequency |
185MHz |
Family |
ABT |
Current - Quiescent (Iq) |
250μA |
Output Characteristics |
3-STATE |
Current - Output High, Low |
32mA 64mA |
Output Polarity |
TRUE |
Max I(ol) |
0.064 A |
Number of Bits per Element |
10 |
Max Propagation Delay @ V, Max CL |
6.2ns @ 5V, 50pF |
Trigger Type |
Positive Edge |
Input Capacitance |
4pF |
Propagation Delay (tpd) |
6.7 ns |
Power Supply Current-Max (ICC) |
38mA |
Height Seated (Max) |
2mm |
Length |
8.2mm |
Width |
5.3mm |
RoHS Status |
ROHS3 Compliant |
74ABT821DB,112 Overview
As a result, it is packaged as 24-SSOP (0.209, 5.30mm Width). Package Tubeembeds it. As configured, the output uses Tri-State, Non-Inverted. It is configured with the trigger Positive Edge. In this case, the electronic component is mounted in the way of Surface Mount. Powered by a 4.5V~5.5Vvolt supply, it operates as follows. -40°C~85°C TAis the operating temperature. It is an electronic flip flop with the type D-Type. It is a type of FPGA belonging to the 74ABT series. It should not exceed 185MHzin its output frequency. D latch consists of 1 elements. As a result, it consumes 250μA quiescent current. In 24terminations, a transmission line is terminated with a JK flip flop that matches its characteristic impedance. JK flip flop belongs to 74ABT821 family. It is powered from a supply voltage of 5V. Its input capacitance is 4pF farads. This D flip flop belongs to the family of ABT. The RS flip flops belongs to FF/Latches base part number. As soon as 5.5Vis reached, Vsup reaches its maximum value. If you want to maintain normal operation, you should keep the supply voltage (Vsup) above 4.5V. It operates from 5V power supplies. The D flip flop is embedded with 2ports. Additionally, you may refer to the D latch's additional POWER OFF DISABLE OUTPUTS TO PERMIT LIVE INSERTION; WITH POWER-UP RESET.
74ABT821DB,112 Features
Tube package
74ABT series
5V power supplies
74ABT821DB,112 Applications
There are a lot of NXP USA Inc. 74ABT821DB,112 Flip Flops applications.
- Memory
- Safety Clamp
- Event Detectors
- Shift registers
- Digital electronics systems
- Balanced 24 mA output drivers
- Frequency Divider circuits
- Test & Measurement
- Circuit Design
- Convert a momentary switch to a toggle switch