74ACT374SJX
| Parameters | |
|---|---|
| Mounting Type | Surface Mount |
| Package / Case | 20-SOIC (0.209, 5.30mm Width) |
| Surface Mount | YES |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Tape & Reel (TR) |
| Series | 74ACT |
| JESD-609 Code | e3 |
| Pbfree Code | yes |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 20 |
| Type | D-Type |
| Terminal Finish | MATTE TIN |
| Technology | CMOS |
| Voltage - Supply | 4.5V~5.5V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 5V |
| Reach Compliance Code | unknown |
| Time@Peak Reflow Temperature-Max (s) | NOT SPECIFIED |
| JESD-30 Code | R-PDSO-G20 |
| Function | Standard |
| Output Type | Tri-State, Non-Inverted |
| Number of Elements | 1 |
| Supply Voltage-Max (Vsup) | 5.5V |
| Supply Voltage-Min (Vsup) | 4.5V |
| Number of Ports | 2 |
| Clock Frequency | 160MHz |
| Family | ACT |
| Current - Quiescent (Iq) | 40μA |
| Output Characteristics | 3-STATE |
| Current - Output High, Low | 24mA 24mA |
| Output Polarity | TRUE |
| Number of Bits per Element | 8 |
| Max Propagation Delay @ V, Max CL | 10ns @ 5V, 50pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 4.5pF |
| Width | 5.3mm |
| RoHS Status | ROHS3 Compliant |
74ACT374SJX Overview
The package is in the form of 20-SOIC (0.209, 5.30mm Width). As part of the package Tape & Reel (TR), it is embedded. T flip flop is configured with an output of Tri-State, Non-Inverted. This trigger is configured to use Positive Edge. Surface Mountis positioned in the way of this electronic part. A voltage of 4.5V~5.5Vis required for its operation. -40°C~85°C TAis the operating temperature. This electronic flip flop is of type D-Type. In FPGA terms, D flip flop is a type of 74ACTseries FPGA. This D flip flop should not have a frequency greater than 160MHz. The list contains 1 elements. As a result, it consumes 40μA quiescent current and is not affected by external forces. There are 20 terminations,A voltage of 5V is used as the power supply for this D latch. JK flip flop input capacitance is 4.5pF farads. In this case, the D flip flop belongs to the ACTfamily. 5.5Vis the maximum supply voltage (Vsup). If you want to maintain normal operation, you should keep the supply voltage (Vsup) above 4.5V. The flip flop contains 2ports.
74ACT374SJX Features
Tape & Reel (TR) package
74ACT series
74ACT374SJX Applications
There are a lot of Rochester Electronics, LLC 74ACT374SJX Flip Flops applications.
- QML qualified product
- Clock pulse
- 2 – Bit synchronous counter
- Safety Clamp
- Pattern generators
- Data storage
- Common Clocks
- Frequency division
- Single Down Count-Control Line
- Circuit Design
