74ACTQ18823SSC
| Parameters | |
|---|---|
| Mounting Type | Surface Mount |
| Package / Case | 56-BSSOP (0.295, 7.50mm Width) |
| Surface Mount | YES |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Tube |
| Series | 74ACTQ |
| JESD-609 Code | e3 |
| Pbfree Code | yes |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 56 |
| Type | D-Type |
| Terminal Finish | MATTE TIN |
| Additional Feature | WITH CLEAR AND CLOCK ENABLE |
| Technology | CMOS |
| Voltage - Supply | 4.5V~5.5V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 5V |
| Terminal Pitch | 0.635mm |
| Time@Peak Reflow Temperature-Max (s) | NOT SPECIFIED |
| JESD-30 Code | R-PDSO-G56 |
| Function | Reset |
| Qualification Status | COMMERCIAL |
| Output Type | Tri-State, Non-Inverted |
| Number of Elements | 2 |
| Supply Voltage-Max (Vsup) | 5.5V |
| Supply Voltage-Min (Vsup) | 4.5V |
| Number of Ports | 2 |
| Clock Frequency | 100MHz |
| Family | ACT |
| Current - Quiescent (Iq) | 80μA |
| Output Characteristics | 3-STATE |
| Current - Output High, Low | 24mA 24mA |
| Output Polarity | TRUE |
| Number of Bits per Element | 9 |
| Max Propagation Delay @ V, Max CL | 9ns @ 5V, 50pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 4.5pF |
| Propagation Delay (tpd) | 10 ns |
| Length | 18.415mm |
| Width | 7.5mm |
| RoHS Status | ROHS3 Compliant |
74ACTQ18823SSC Overview
The item is packaged in 56-BSSOP (0.295, 7.50mm Width)cases. There is an embedded version in the package Tube. The output it is configured with uses Tri-State, Non-Inverted. It is configured with a trigger that uses a value of Positive Edge. The electronic part is mounted in the way of Surface Mount. It operates with a supply voltage of 4.5V~5.5V. The operating temperature is -40°C~85°C TA. Logic flip flops of this type are classified as D-Type. FPGAs belonging to the 74ACTQseries contain this type of chip. It should not exceed 100MHzin terms of its output frequency. In total, there are 2 elements. Despite external influences, it consumes 80μAof quiescent current. The number of terminations is 56. An input voltage of 5Vpowers the D latch. JK flip flop input capacitance is 4.5pF farads. An electronic device belonging to the family ACTcan be found here. As soon as Vsup reaches 5.5V, the maximum supply voltage is reached. For normal operation, the supply voltage (Vsup) should be above 4.5V. The D flip flop is embedded with 2ports. As an additional reference, you may refer to electronic flip flop WITH CLEAR AND CLOCK ENABLE.
74ACTQ18823SSC Features
Tube package
74ACTQ series
74ACTQ18823SSC Applications
There are a lot of Rochester Electronics, LLC 74ACTQ18823SSC Flip Flops applications.
- Test & Measurement
- Safety Clamp
- Digital electronics systems
- Shift Registers
- Matched Rise and Fall
- High Performance Logic for test systems
- Circuit Design
- Frequency Divider circuits
- Storage Registers
- Bounce elimination switch
