74AUP1G74GD,125
| Parameters | |
|---|---|
| Contact Plating | Gold |
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 8-XFDFN |
| Number of Pins | 8 |
| Operating Temperature | -40°C~125°C TA |
| Packaging | Tape & Reel (TR) |
| Series | 74AUP |
| JESD-609 Code | e4 |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 8 |
| Type | D-Type |
| Technology | CMOS |
| Voltage - Supply | 0.8V~3.6V |
| Terminal Position | DUAL |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 1.2V |
| Terminal Pitch | 0.5mm |
| Time@Peak Reflow Temperature-Max (s) | 40 |
| Base Part Number | 74AUP1G74 |
| Function | Set(Preset) and Reset |
| Output Type | Differential |
| Polarity | Non-Inverting |
| Supply Voltage-Max (Vsup) | 3.6V |
| Number of Bits | 1 |
| Clock Frequency | 315MHz |
| Propagation Delay | 22.5 ns |
| Quiescent Current | 500nA |
| Turn On Delay Time | 2.2 ns |
| Family | AUP/ULP/V |
| Logic Function | AND, D-Type |
| Current - Output High, Low | 4mA 4mA |
| Max Propagation Delay @ V, Max CL | 5.8ns @ 3.3V, 30pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 0.6pF |
| Number of Input Lines | 1 |
| Clock Edge Trigger Type | Positive Edge |
| Height Seated (Max) | 0.5mm |
| Length | 3mm |
| Width | 2mm |
| Radiation Hardening | No |
| RoHS Status | RoHS Compliant |
| Lead Free | Lead Free |
74AUP1G74GD,125 Overview
8-XFDFNis the way it is packaged. The package Tape & Reel (TR)contains it. This output is configured with Differential. The trigger configured with it uses Positive Edge. Surface Mountis positioned in the way of this electronic part. The supply voltage is set to 0.8V~3.6V. Currently, the operating temperature is -40°C~125°C TA. It is an electronic flip flop with the type D-Type. In terms of FPGAs, it belongs to the 74AUP series. It should not exceed 315MHzin its output frequency. A total of 8 terminations have been made. It is a member of the 74AUP1G74 family. A voltage of 1.2V is used to power it. There is 0.6pF input capacitance for this T flip flop. In terms of electronic devices, this device belongs to the AUP/ULP/Vfamily of devices. This electronic part is mounted in the way of Surface Mount. A total of 8pins are provided on this board. This device exhibits a clock edge trigger type of Positive Edge. An electronic part designed with 1bits is used in this application. 3.6Vis the maximum supply voltage (Vsup). It is reported that there are 1 input lines. In terms of quiescent current, it consumes 500nA .
74AUP1G74GD,125 Features
Tape & Reel (TR) package
74AUP series
8 pins
1 Bits
74AUP1G74GD,125 Applications
There are a lot of Nexperia USA Inc. 74AUP1G74GD,125 Flip Flops applications.
- Latch
- QML qualified product
- Power down protection
- Bounce elimination switch
- Buffered Clock
- Guaranteed simultaneous switching noise level
- Synchronous counter
- Common Clocks
- Buffer registers
- Data storage
