74HC109DB,118
| Parameters | |
|---|---|
| Factory Lead Time | 1 Week |
| Contact Plating | Gold |
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 16-SSOP (0.209, 5.30mm Width) |
| Number of Pins | 16 |
| Operating Temperature | -40°C~125°C TA |
| Packaging | Tape & Reel (TR) |
| Published | 1997 |
| Series | 74HC |
| JESD-609 Code | e4 |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 16 |
| Type | JK Type |
| Technology | CMOS |
| Voltage - Supply | 2V~6V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 4.5V |
| Terminal Pitch | 0.65mm |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Base Part Number | 74HC109 |
| Function | Set(Preset) and Reset |
| Output Type | Differential |
| Operating Supply Voltage | 5V |
| Polarity | Non-Inverting |
| Supply Voltage-Max (Vsup) | 6V |
| Supply Voltage-Min (Vsup) | 2V |
| Number of Circuits | 2 |
| Load Capacitance | 50pF |
| Clock Frequency | 81MHz |
| Propagation Delay | 15 ns |
| Quiescent Current | 4μA |
| Turn On Delay Time | 9 ns |
| Family | HC/UH |
| Logic Function | AND, Flip-Flop, JK-Type |
| Current - Output High, Low | 5.2mA 5.2mA |
| Number of Bits per Element | 1 |
| Max Propagation Delay @ V, Max CL | 30ns @ 6V, 50pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 3.5pF |
| Clock Edge Trigger Type | Positive Edge |
| Width | 5.3mm |
| Radiation Hardening | No |
| RoHS Status | ROHS3 Compliant |
74HC109DB,118 Overview
It is packaged in the way of 16-SSOP (0.209, 5.30mm Width). A package named Tape & Reel (TR)includes it. T flip flop uses Differentialas the output. It is configured with a trigger that uses a value of Positive Edge. There is an electrical part that is mounted in the way of Surface Mount. The supply voltage is set to 2V~6V. It is operating at a temperature of -40°C~125°C TA. JK Typedescribes this flip flop. It is a type of FPGA belonging to the 74HC series. Its output frequency should not exceed 81MHz Hz. There are 16 terminations, which are the practice of ending a transmission line with a device that matches the characteristic impedance of the line. It is a member of the 74HC109 family. A voltage of 4.5V is used as the power supply for this D latch. The input capacitance of this T flip flop is 3.5pF farads, which is defined as the capacitance between the input terminals of an op amp with either input grounded. A device of this type belongs to the family of HC/UH. There is an electronic component mounted in the way of Surface Mount. The 16pins are designed into the board. The clock edge trigger type for this device is Positive Edge. As soon as 6Vis reached, Vsup reaches its maximum value. For normal operation, the supply voltage (Vsup) should be kept above 2V. Its flexibility is enhanced by 2 circuits. If high efficiency is to be achieved, the supply voltage should be maintained at 5V. This D latch consumes 4μA quiescent current at all.
74HC109DB,118 Features
Tape & Reel (TR) package
74HC series
16 pins
74HC109DB,118 Applications
There are a lot of Nexperia USA Inc. 74HC109DB,118 Flip Flops applications.
- Latch
- Consumer
- Cold spare funcion
- Set-reset capability
- Event Detectors
- Matched Rise and Fall
- EMI reduction circuitry
- Balanced 24 mA output drivers
- Shift Registers
- Data Synchronizers
