74HC112N,652
| Parameters | |
|---|---|
| Mounting Type | Through Hole |
| Package / Case | 16-DIP (0.300, 7.62mm) |
| Surface Mount | NO |
| Operating Temperature | -40°C~125°C TA |
| Packaging | Tube |
| Published | 1998 |
| Series | 74HC |
| JESD-609 Code | e4 |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 16 |
| Type | JK Type |
| Terminal Finish | NICKEL PALLADIUM GOLD |
| Subcategory | FF/Latches |
| Technology | CMOS |
| Voltage - Supply | 2V~6V |
| Terminal Position | DUAL |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 4.5V |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Base Part Number | 74HC112 |
| Function | Set(Preset) and Reset |
| Qualification Status | Not Qualified |
| Output Type | Differential |
| Number of Elements | 2 |
| Supply Voltage-Max (Vsup) | 6V |
| Supply Voltage-Min (Vsup) | 2V |
| Load Capacitance | 50pF |
| Clock Frequency | 71MHz |
| Family | HC/UH |
| Current - Quiescent (Iq) | 4μA |
| Current - Output High, Low | 5.2mA 5.2mA |
| Output Polarity | COMPLEMENTARY |
| Max I(ol) | 0.004 A |
| Number of Bits per Element | 1 |
| Max Propagation Delay @ V, Max CL | 30ns @ 6V, 50pF |
| Trigger Type | Negative Edge |
| Input Capacitance | 3.5pF |
| Height Seated (Max) | 4.7mm |
| RoHS Status | ROHS3 Compliant |
74HC112N,652 Overview
The item is packaged in 16-DIP (0.300, 7.62mm)cases. It is contained within the Tubepackage. As configured, the output uses Differential. The trigger it is configured with uses Negative Edge. This electronic part is mounted in the way of Through Hole. A voltage of 2V~6Vis used as the supply voltage. In this case, the operating temperature is -40°C~125°C TA. A flip flop of this type is classified as a JK Type. In this case, it is a type of FPGA belonging to the 74HC series. In order for it to function properly, its output frequency should not exceed 71MHz. D latch consists of 2 elements. T flip flop consumes 4μA quiescent energy. There are 16 terminations, which are the practice of ending a transmission line with a device that matches the characteristic impedance of the line. If you search by 74HC112, you will find similar parts. The D flip flop is powered by a voltage of 4.5V . The input capacitance of this T flip flop is 3.5pF farads, which is defined as the capacitance between the input terminals of an op amp with either input grounded. It is a member of the HC/UHfamily of D flip flop. The part is included in FF/Latches. There is a 6Vmaximum supply voltage (Vsup). It is imperative that the supply voltage (Vsup) is maintained above 2Vin order to ensure normal operation.
74HC112N,652 Features
Tube package
74HC series
74HC112N,652 Applications
There are a lot of NXP USA Inc. 74HC112N,652 Flip Flops applications.
- Computing
- EMI reduction circuitry
- Safety Clamp
- Automotive
- Common Clocks
- Synchronous counter
- Consumer
- Shift registers
- Bounce elimination switch
- Data transfer
