74HC273PW,112
| Parameters | |
|---|---|
| Factory Lead Time | 1 Week |
| Mounting Type | Surface Mount |
| Package / Case | 20-TSSOP (0.173, 4.40mm Width) |
| Surface Mount | YES |
| Operating Temperature | -40°C~125°C TA |
| Packaging | Tube |
| Published | 2001 |
| Series | 74HC |
| JESD-609 Code | e4 |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 20 |
| Type | D-Type |
| Terminal Finish | Nickel/Palladium/Gold (Ni/Pd/Au) |
| Technology | CMOS |
| Voltage - Supply | 2V~6V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 5V |
| Terminal Pitch | 0.65mm |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Base Part Number | 74HC273 |
| JESD-30 Code | R-PDSO-G20 |
| Function | Master Reset |
| Qualification Status | Not Qualified |
| Output Type | Non-Inverted |
| Number of Elements | 1 |
| Supply Voltage-Max (Vsup) | 6V |
| Supply Voltage-Min (Vsup) | 2V |
| Load Capacitance | 50pF |
| Clock Frequency | 122MHz |
| Family | HC/UH |
| Current - Quiescent (Iq) | 8μA |
| Current - Output High, Low | 5.2mA 5.2mA |
| Output Polarity | TRUE |
| Number of Bits per Element | 8 |
| Max Propagation Delay @ V, Max CL | 26ns @ 6V, 50pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 3.5pF |
| Propagation Delay (tpd) | 225 ns |
| fmax-Min | 24 MHz |
| Length | 6.5mm |
| Width | 4.4mm |
| RoHS Status | ROHS3 Compliant |
74HC273PW,112 Overview
It is packaged in the way of 20-TSSOP (0.173, 4.40mm Width). A package named Tubeincludes it. T flip flop uses Non-Invertedas its output configuration. The trigger it is configured with uses Positive Edge. There is an electronic component mounted in the way of Surface Mount. The JK flip flop operates with an input voltage of 2V~6V volts. Currently, the operating temperature is -40°C~125°C TA. This logic flip flop is classified as type D-Type. The FPGA belongs to the 74HC series. You should not exceed 122MHzin its output frequency. D latch consists of 1 elements. There is 8μA quiescent consumption. There are 20 terminations,D latch belongs to the 74HC273 family. Power is supplied from a voltage of 5V volts. JK flip flop input capacitance is 3.5pF farads. In this case, the D flip flop belongs to the HC/UHfamily. It reaches the maximum supply voltage (Vsup) at 6V. Keeping the supply voltage (Vsup) above 2V is necessary for normal operation.
74HC273PW,112 Features
Tube package
74HC series
74HC273PW,112 Applications
There are a lot of Nexperia USA Inc. 74HC273PW,112 Flip Flops applications.
- Shift Registers
- Circuit Design
- Asynchronous counter
- Digital electronics systems
- Count Modes
- Balanced 24 mA output drivers
- High Performance Logic for test systems
- Matched Rise and Fall
- Data storage
- ATE
