74HC564N,652
| Parameters | |
|---|---|
| Mounting Type | Through Hole |
| Package / Case | 20-DIP (0.300, 7.62mm) |
| Surface Mount | NO |
| Operating Temperature | -40°C~125°C TA |
| Packaging | Tube |
| Series | 74HC |
| JESD-609 Code | e4 |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 20 |
| Type | D-Type |
| Terminal Finish | Nickel/Palladium/Gold (Ni/Pd/Au) |
| Additional Feature | BROADSIDE VERSION OF 534 |
| Subcategory | FF/Latches |
| Technology | CMOS |
| Voltage - Supply | 2V~6V |
| Terminal Position | DUAL |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 5V |
| Terminal Pitch | 2.54mm |
| Reach Compliance Code | unknown |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Base Part Number | 74HC564 |
| JESD-30 Code | R-PDIP-T20 |
| Function | Standard |
| Qualification Status | Not Qualified |
| Output Type | Tri-State, Inverted |
| Number of Elements | 1 |
| Supply Voltage-Max (Vsup) | 6V |
| Power Supplies | 2/6V |
| Supply Voltage-Min (Vsup) | 2V |
| Load Capacitance | 50pF |
| Number of Ports | 2 |
| Clock Frequency | 137MHz |
| Family | HC/UH |
| Current - Quiescent (Iq) | 8μA |
| Output Characteristics | 3-STATE |
| Current - Output High, Low | 7.8mA 7.8mA |
| Max I(ol) | 0.006 A |
| Number of Bits per Element | 8 |
| Max Propagation Delay @ V, Max CL | 28ns @ 6V, 50pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 3.5pF |
| Propagation Delay (tpd) | 250 ns |
| Max Frequency@Nom-Sup | 24000000Hz |
| Height Seated (Max) | 4.2mm |
| Length | 26.73mm |
| Width | 7.62mm |
| RoHS Status | ROHS3 Compliant |
74HC564N,652 Overview
In the form of 20-DIP (0.300, 7.62mm), it has been packaged. There is an embedded version in the package Tube. In the configuration, Tri-State, Invertedis used as the output. This trigger is configured to use Positive Edge. There is an electronic component mounted in the way of Through Hole. The supply voltage is set to 2V~6V. It is operating at -40°C~125°C TA. A flip flop of this type is classified as a D-Type. In this case, it is a type of FPGA belonging to the 74HC series. Its output frequency should not exceed 137MHz Hz. D latch consists of 1 elements. This process consumes 8μA quiescents. The number of terminations is 20. JK flip flop belongs to 74HC564 family. It is powered by a voltage of 5V . The input capacitance of this T flip flop is 3.5pF farads, which is defined as the capacitance between the input terminals of an op amp with either input grounded. The electronic device belongs to the HC/UHfamily. It is included in FF/Latches. It reaches 6Vwhen the maximum supply voltage (Vsup) is applied. The supply voltage (Vsup) should be maintained above 2V for normal operation. The system runs on a power supply of 2/6V watts. There are 2 terminations, which are the practice of ending a transmission line with a device that matches the characteristic impedance of the line. In addition, BROADSIDE VERSION OF 534is a characteristic of it.
74HC564N,652 Features
Tube package
74HC series
2/6V power supplies
74HC564N,652 Applications
There are a lot of NXP USA Inc. 74HC564N,652 Flip Flops applications.
- Matched Rise and Fall
- ESD protection
- Functionally equivalent to the MC10/100EL29
- Frequency Divider circuits
- Latch-up performance
- Cold spare funcion
- Computers
- Instrumentation
- ATE
- Data transfer
