74LCX374SJ
| Parameters | |
|---|---|
| Clock Edge Trigger Type | Positive Edge |
| RoHS Status | RoHS Compliant |
| Lead Free | Lead Free |
| Contact Plating | Tin |
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 20-SOIC (0.209, 5.30mm Width) |
| Number of Pins | 20 |
| Weight | 481.5mg |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Tube |
| Published | 2009 |
| Series | 74LCX |
| JESD-609 Code | e3 |
| Pbfree Code | yes |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 20 |
| ECCN Code | EAR99 |
| Type | D-Type |
| Subcategory | FF/Latches |
| Packing Method | RAIL |
| Technology | CMOS |
| Voltage - Supply | 2V~3.6V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | NOT SPECIFIED |
| Supply Voltage | 2.5V |
| Time@Peak Reflow Temperature-Max (s) | NOT SPECIFIED |
| Base Part Number | 74LCX374 |
| Function | Standard |
| Qualification Status | Not Qualified |
| Output Type | Tri-State, Non-Inverted |
| Number of Elements | 1 |
| Polarity | Non-Inverting |
| Supply Voltage-Min (Vsup) | 2V |
| Number of Circuits | 8 |
| Load Capacitance | 50pF |
| Number of Ports | 2 |
| Number of Bits | 8 |
| Clock Frequency | 150MHz |
| Propagation Delay | 9.5 ns |
| Quiescent Current | 10μA |
| Turn On Delay Time | 8.5 ns |
| Family | LVC/LCX/Z |
| Logic Function | D-Type, Flip-Flop |
| Current - Output High, Low | 24mA 24mA |
| Max I(ol) | 0.024 A |
| Max Propagation Delay @ V, Max CL | 8.5ns @ 3.3V, 50pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 7pF |
| Number of Output Lines | 3 |
74LCX374SJ Overview
In the form of 20-SOIC (0.209, 5.30mm Width), it has been packaged. As part of the package Tube, it is embedded. The output it is configured with uses Tri-State, Non-Inverted. It is configured with the trigger Positive Edge. It is mounted in the way of Surface Mount. The JK flip flop operates at a voltage of 2V~3.6V. Temperature is set to -40°C~85°C TA. D-Typedescribes this flip flop. This type of FPGA is a part of the 74LCX series. Its output frequency should not exceed 150MHz Hz. A total of 1elements are contained within it. There are 20 terminations, which are the practice of ending a transmission line with a device that matches the characteristic impedance of the line. It is a member of the 74LCX374 family. An input voltage of 2.5Vpowers the D latch. The input capacitance of this JK flip flopis 7pF farads. This D flip flop belongs to the family of LVC/LCX/Z. In this case, the electronic component is mounted in the way of Surface Mount. It is designed with 20 pins. This device has Positive Edgeas its clock edge trigger type. There is a base part number FF/Latchesfor the RS flip flops. It is designed with a number of bits of 8. For normal operation, the supply voltage (Vsup) should be kept above 2V. Its flexibility is enhanced by 8 circuits. In view of its reliability, this D flip flop is a good fit for RAIL. The flip flop contains 2ports. To operate, the chip has a total of 3 output lines. As a result, it consumes 10μA of quiescent current without being affected by external factors.
74LCX374SJ Features
Tube package
74LCX series
20 pins
8 Bits
74LCX374SJ Applications
There are a lot of ON Semiconductor 74LCX374SJ Flip Flops applications.
- Computing
- Guaranteed simultaneous switching noise level
- Memory
- Control circuits
- Single Up Count-Control Line
- Count Modes
- Cold spare funcion
- Communications
- Memory
- Buffer registers
