74LV174N,112
| Parameters | |
|---|---|
| Mounting Type | Through Hole |
| Package / Case | 16-DIP (0.300, 7.62mm) |
| Surface Mount | NO |
| Operating Temperature | -40°C~125°C TA |
| Packaging | Tube |
| Published | 1998 |
| Series | 74LV |
| JESD-609 Code | e4 |
| Pbfree Code | yes |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 16 |
| Type | D-Type |
| Terminal Finish | Nickel/Palladium/Gold (Ni/Pd/Au) |
| Subcategory | FF/Latches |
| Technology | CMOS |
| Voltage - Supply | 1V~5.5V |
| Terminal Position | DUAL |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 3.3V |
| Terminal Pitch | 2.54mm |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Base Part Number | 74LV174 |
| Function | Master Reset |
| Qualification Status | Not Qualified |
| Output Type | Non-Inverted |
| Number of Elements | 1 |
| Supply Voltage-Max (Vsup) | 5.5V |
| Power Supplies | 3.3V |
| Supply Voltage-Min (Vsup) | 1V |
| Load Capacitance | 50pF |
| Clock Frequency | 100MHz |
| Family | LV/LV-A/LVX/H |
| Current - Quiescent (Iq) | 160μA |
| Current - Output High, Low | 12mA 12mA |
| Output Polarity | TRUE |
| Number of Bits per Element | 6 |
| Max Propagation Delay @ V, Max CL | 21ns @ 5V, 50pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 3.5pF |
| fmax-Min | 20 MHz |
| Max Frequency@Nom-Sup | 20000000Hz |
| Height Seated (Max) | 4.2mm |
| RoHS Status | ROHS3 Compliant |
74LV174N,112 Overview
The flip flop is packaged in a case of 16-DIP (0.300, 7.62mm). D flip flop is embedded in the Tube package. T flip flop uses Non-Invertedas its output configuration. The trigger it is configured with uses Positive Edge. The electronic part is mounted in the way of Through Hole. The supply voltage is set to 1V~5.5V. A temperature of -40°C~125°C TAis considered to be the operating temperature. It is an electronic flip flop with the type D-Type. In this case, it is a type of FPGA belonging to the 74LV series. There should be no greater frequency than 100MHzon its output. In total, there are 1 elements. It consumes 160μA of quiescent current without being affected by external factors. It has been determined that there have been 16 terminations. JK flip flop belongs to 74LV174 family. It is powered by a voltage of 3.3V . A JK flip flop with a 3.5pFfarad input capacitance is used here. This D flip flop belongs to the family of LV/LV-A/LVX/H. There is a base part number FF/Latchesfor the RS flip flops. There is a 5.5Vmaximum supply voltage (Vsup). The supply voltage (Vsup) should be maintained above 1V for normal operation. A total of 3.3V power supplies are needed to run it.
74LV174N,112 Features
Tube package
74LV series
3.3V power supplies
74LV174N,112 Applications
There are a lot of NXP USA Inc. 74LV174N,112 Flip Flops applications.
- Frequency division
- Communications
- Automotive
- Bus hold
- Cold spare funcion
- Computers
- Single Down Count-Control Line
- Count Modes
- EMI reduction circuitry
- Matched Rise and Fall
