74LV174PW,118
| Parameters | |
|---|---|
| Mounting Type | Surface Mount |
| Package / Case | 16-TSSOP (0.173, 4.40mm Width) |
| Supplier Device Package | 16-TSSOP |
| Operating Temperature | -40°C~125°C TA |
| Packaging | Tape & Reel (TR) |
| Series | 74LV |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Type | D-Type |
| Voltage - Supply | 1V~5.5V |
| Function | Master Reset |
| Output Type | Non-Inverted |
| Number of Elements | 1 |
| Clock Frequency | 100MHz |
| Current - Quiescent (Iq) | 160μA |
| Current - Output High, Low | 12mA 12mA |
| Number of Bits per Element | 6 |
| Max Propagation Delay @ V, Max CL | 21ns @ 5V, 50pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 3.5pF |
| RoHS Status | ROHS3 Compliant |
74LV174PW,118 Overview
The item is packaged in 16-TSSOP (0.173, 4.40mm Width)cases. It is included in the package Tape & Reel (TR). Currently, the output is configured to use Non-Inverted. This trigger is configured to use Positive Edge. The electronic part is mounted in the way of Surface Mount. It operates with a supply voltage of 1V~5.5V. Currently, the operating temperature is -40°C~125°C TA. This D latch has the type D-Type. In FPGA terms, D flip flop is a type of 74LVseries FPGA. A frequency of 100MHzshould be the maximum output frequency. In total, it contains 1 elements. There is 160μA quiescent consumption. The input capacitance of this T flip flop is 3.5pF farads, which is defined as the capacitance between the input terminals of an op amp with either input grounded.
74LV174PW,118 Features
Tape & Reel (TR) package
74LV series
74LV174PW,118 Applications
There are a lot of Rochester Electronics, LLC 74LV174PW,118 Flip Flops applications.
- Frequency Dividers
- Common Clocks
- Single Down Count-Control Line
- Asynchronous counter
- Safety Clamp
- EMI reduction circuitry
- Power down protection
- Patented noise
- Test & Measurement
- Clock pulse
