74LV377PW,112
| Parameters | |
|---|---|
| Mounting Type | Surface Mount |
| Package / Case | 20-TSSOP (0.173, 4.40mm Width) |
| Surface Mount | YES |
| Operating Temperature | -40°C~125°C TA |
| Packaging | Tube |
| Published | 1998 |
| Series | 74LV |
| JESD-609 Code | e4 |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 20 |
| Type | D-Type |
| Terminal Finish | Nickel/Palladium/Gold (Ni/Pd/Au) |
| Additional Feature | WITH HOLD MODE |
| Subcategory | FF/Latches |
| Technology | CMOS |
| Voltage - Supply | 1V~3.6V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 3.3V |
| Terminal Pitch | 0.65mm |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Base Part Number | 74LV377 |
| JESD-30 Code | R-PDSO-G20 |
| Function | Standard |
| Qualification Status | Not Qualified |
| Output Type | Non-Inverted |
| Number of Elements | 1 |
| Supply Voltage-Max (Vsup) | 5.5V |
| Power Supplies | 3.3V |
| Supply Voltage-Min (Vsup) | 1V |
| Load Capacitance | 50pF |
| Clock Frequency | 70MHz |
| Family | LV/LV-A/LVX/H |
| Current - Quiescent (Iq) | 20μA |
| Current - Output High, Low | 6mA 6mA |
| Output Polarity | TRUE |
| Number of Bits per Element | 8 |
| Max Propagation Delay @ V, Max CL | 30ns @ 3.3V, 50pF |
| Prop. Delay@Nom-Sup | 36 ns |
| Trigger Type | Positive Edge |
| Input Capacitance | 3.5pF |
| Propagation Delay (tpd) | 36 ns |
| fmax-Min | 20 MHz |
| Max Frequency@Nom-Sup | 20000000Hz |
| Length | 6.5mm |
| Width | 4.4mm |
| RoHS Status | ROHS3 Compliant |
74LV377PW,112 Overview
As a result, it is packaged as 20-TSSOP (0.173, 4.40mm Width). Package Tubeembeds it. T flip flop uses Non-Invertedas the output. This trigger uses the value Positive Edge. There is an electrical part that is mounted in the way of Surface Mount. The JK flip flop operates with an input voltage of 1V~3.6V volts. It is operating at a temperature of -40°C~125°C TA. This electronic flip flop is of type D-Type. FPGAs belonging to the 74LVseries contain this type of chip. A frequency of 70MHzshould be the maximum output frequency. In total, it contains 1 elements. It consumes 20μA of quiescent In 20terminations, a transmission line is terminated with a JK flip flop that matches its characteristic impedance. The 74LV377family includes it. The D flip flop is powered by a voltage of 3.3V . The input capacitance of this T flip flop is 3.5pF farads, which is defined as the capacitance between the input terminals of an op amp with either input grounded. The electronic device belongs to the LV/LV-A/LVX/Hfamily. There is a FF/Latchesbase part number assigned to the RS flip flops. Vsup reaches its maximum value at 5.5V. Normal operation requires a supply voltage (Vsup) above 1V. The D latch operates on 3.3V volts. Additionally, there are WITH HOLD MODE on the electronic flip flop that can be referred to.
74LV377PW,112 Features
Tube package
74LV series
3.3V power supplies
74LV377PW,112 Applications
There are a lot of NXP USA Inc. 74LV377PW,112 Flip Flops applications.
- Synchronous counter
- Balanced 24 mA output drivers
- Frequency Divider circuits
- Power down protection
- Memory
- Single Up Count-Control Line
- Cold spare funcion
- Matched Rise and Fall
- Supports Live Insertion
- Clock pulse
