74LVC109DB,118
| Parameters | |
|---|---|
| Mounting Type | Surface Mount |
| Package / Case | 16-SSOP (0.209, 5.30mm Width) |
| Surface Mount | YES |
| Operating Temperature | -40°C~125°C TA |
| Packaging | Tape & Reel (TR) |
| Published | 2002 |
| Series | 74LVC |
| JESD-609 Code | e4 |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 16 |
| Type | JK Type |
| Terminal Finish | Nickel/Palladium/Gold (Ni/Pd/Au) |
| Technology | CMOS |
| Voltage - Supply | 1.65V~3.6V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 3.3V |
| Terminal Pitch | 0.65mm |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Base Part Number | 74LVC109 |
| Function | Set(Preset) and Reset |
| Qualification Status | Not Qualified |
| Output Type | Differential |
| Number of Elements | 2 |
| Supply Voltage-Max (Vsup) | 3.6V |
| Load Capacitance | 50pF |
| Clock Frequency | 330MHz |
| Family | LVC/LCX/Z |
| Current - Quiescent (Iq) | 10μA |
| Current - Output High, Low | 24mA 24mA |
| Output Polarity | COMPLEMENTARY |
| Number of Bits per Element | 1 |
| Max Propagation Delay @ V, Max CL | 6.8ns @ 3.3V, 50pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 5pF |
| Propagation Delay (tpd) | 7.5 ns |
| Width | 5.3mm |
| RoHS Status | ROHS3 Compliant |
74LVC109DB,118 Overview
It is packaged in the way of 16-SSOP (0.209, 5.30mm Width). You can find it in the Tape & Reel (TR)package. Currently, the output is configured to use Differential. The trigger configured with it uses Positive Edge. It is mounted in the way of Surface Mount. A voltage of 1.65V~3.6Vis required for its operation. A temperature of -40°C~125°C TAis considered to be the operating temperature. This logic flip flop is classified as type JK Type. JK flip flop belongs to the 74LVCseries of FPGAs. There should be no greater frequency than 330MHzon its output. In total, there are 2 elements. There is 10μA quiescent consumption. There are 16 terminations, which are the practice of ending a transmission line with a device that matches the characteristic impedance of the line. If you search by 74LVC109, you will find similar parts. A voltage of 3.3V provides power to the D latch. The input capacitance of this T flip flop is 5pF farads, which is defined as the capacitance between the input terminals of an op amp with either input grounded. It is a member of the LVC/LCX/Zfamily of D flip flop. 3.6Vis the maximum supply voltage (Vsup).
74LVC109DB,118 Features
Tape & Reel (TR) package
74LVC series
74LVC109DB,118 Applications
There are a lot of NXP USA Inc. 74LVC109DB,118 Flip Flops applications.
- ATE
- CMOS Process
- Divide a clock signal by 2 or 4
- Computers
- Latch-up performance
- Data storage
- Digital electronics systems
- Modulo – n – counter
- Balanced 24 mA output drivers
- Buffer registers
