74LVC1G175GW,165
| Parameters | |
|---|---|
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 6-TSSOP, SC-88, SOT-363 |
| Number of Pins | 6 |
| Operating Temperature | -40°C~125°C TA |
| Packaging | Tape & Reel (TR) |
| Published | 2014 |
| Series | 74LVC |
| JESD-609 Code | e3 |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 6 |
| Type | D-Type |
| Terminal Finish | TIN |
| Subcategory | FF/Latches |
| Packing Method | TAPE AND REEL |
| Technology | CMOS |
| Voltage - Supply | 1.65V~5.5V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 2.7V |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Base Part Number | 74LVC1G175 |
| Function | Reset |
| Qualification Status | Not Qualified |
| Output Type | Non-Inverted |
| Number of Elements | 1 |
| Supply Voltage-Max (Vsup) | 5.5V |
| Power Supplies | 3.3V |
| Load Capacitance | 50pF |
| Number of Bits | 1 |
| Clock Frequency | 200MHz |
| Turn On Delay Time | 2.2 ns |
| Family | LVC/LCX/Z |
| Current - Quiescent (Iq) | 10μA |
| Current - Output High, Low | 32mA 32mA |
| Output Polarity | TRUE |
| Max I(ol) | 0.024 A |
| Max Propagation Delay @ V, Max CL | 4ns @ 5V, 50pF |
| Prop. Delay@Nom-Sup | 7.5 ns |
| Trigger Type | Positive Edge |
| Input Capacitance | 2.5pF |
| fmax-Min | 200 MHz |
| Clock Edge Trigger Type | Positive Edge |
| Length | 2mm |
| RoHS Status | RoHS Compliant |
74LVC1G175GW,165 Overview
The flip flop is packaged in a case of 6-TSSOP, SC-88, SOT-363. There is an embedded version in the package Tape & Reel (TR). The output it is configured with uses Non-Inverted. This trigger is configured to use Positive Edge. In this case, the electronic component is mounted in the way of Surface Mount. The JK flip flop operates at a voltage of 1.65V~5.5V. In the operating environment, the temperature is -40°C~125°C TA. This D latch has the type D-Type. FPGAs belonging to the 74LVCseries contain this type of chip. There should be no greater frequency than 200MHzon its output. In total, there are 1 elements. Despite external influences, it consumes 10μAof quiescent current. There are 6 terminations, which are the practice of ending a transmission line with a device that matches the characteristic impedance of the line. The 74LVC1G175family includes it. Power is provided by a 2.7V supply. A 2.5pFfarad input capacitance is provided by this T flip flop. It is a member of the LVC/LCX/Zfamily of D flip flop. A part of the electronic system is mounted in the way of Surface Mount. This board has 6 pins. This device has the clock edge trigger type of Positive Edge. It is part of the FF/Latchesbase part number family. This flip flop is designed with 1 Bits. 5.5Vis the maximum supply voltage (Vsup). In light of its reliable performance, this T flip flop is well suited for TAPE AND REEL. A total of 3.3V power supplies are needed to run it.
74LVC1G175GW,165 Features
Tape & Reel (TR) package
74LVC series
6 pins
1 Bits
3.3V power supplies
74LVC1G175GW,165 Applications
There are a lot of Nexperia USA Inc. 74LVC1G175GW,165 Flip Flops applications.
- Storage registers
- Asynchronous counter
- Data storage
- Count Modes
- Single Down Count-Control Line
- Power down protection
- Buffered Clock
- Computers
- Common Clocks
- Automotive
