74LVC377DB,112
| Parameters | |
|---|---|
| Factory Lead Time | 1 Week |
| Contact Plating | Gold |
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 20-SSOP (0.209, 5.30mm Width) |
| Number of Pins | 20 |
| Operating Temperature | -40°C~125°C TA |
| Packaging | Tube |
| Series | 74LVC |
| JESD-609 Code | e4 |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 20 |
| Type | D-Type |
| Additional Feature | WITH HOLD MODE |
| Technology | CMOS |
| Voltage - Supply | 1.65V~3.6V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 2.7V |
| Terminal Pitch | 0.65mm |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Base Part Number | 74LVC377 |
| Function | Standard |
| Output Type | Non-Inverted |
| Number of Elements | 1 |
| Polarity | Non-Inverting |
| Supply Voltage-Max (Vsup) | 3.6V |
| Number of Bits | 8 |
| Clock Frequency | 330MHz |
| Propagation Delay | 6 ns |
| Quiescent Current | 100nA |
| Turn On Delay Time | 1.5 ns |
| Family | LVC/LCX/Z |
| Logic Function | D-Type, Flip-Flop |
| Current - Quiescent (Iq) | 10μA |
| Current - Output High, Low | 24mA 24mA |
| Max Propagation Delay @ V, Max CL | 7.6ns @ 3.3V, 50pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 5pF |
| Number of Input Lines | 8 |
| Clock Edge Trigger Type | Positive Edge |
| Height Seated (Max) | 2mm |
| Length | 7.2mm |
| Width | 5.3mm |
| Radiation Hardening | No |
| RoHS Status | ROHS3 Compliant |
74LVC377DB,112 Overview
20-SSOP (0.209, 5.30mm Width)is the way it is packaged. There is an embedded version in the package Tube. This output is configured with Non-Inverted. It is configured with a trigger that uses a value of Positive Edge. It is mounted in the way of Surface Mount. The JK flip flop operates at 1.65V~3.6Vvolts. Currently, the operating temperature is -40°C~125°C TA. D-Typedescribes this flip flop. JK flip flop belongs to the 74LVCseries of FPGAs. A frequency of 330MHzshould be the maximum output frequency. D latch consists of 1 elements. T flip flop consumes 10μA quiescent energy. The number of terminations is 20. Members of the 74LVC377family make up this object. A voltage of 2.7V provides power to the D latch. Its input capacitance is 5pFfarads. Electronic devices of this type belong to the LVC/LCX/Zfamily. This electronic part is mounted in the way of Surface Mount. The electronic flip flop is designed with pins 20. This device has the clock edge trigger type of Positive Edge. 8bits are used in its design. Vsup reaches 3.6V, the maximal supply voltage. A total of 8input lines have been provided. In terms of quiescent current, it consumes 100nA . As an additional reference, you may refer to electronic flip flop WITH HOLD MODE.
74LVC377DB,112 Features
Tube package
74LVC series
20 pins
8 Bits
74LVC377DB,112 Applications
There are a lot of Nexperia USA Inc. 74LVC377DB,112 Flip Flops applications.
- Memory
- Buffered Clock
- Convert a momentary switch to a toggle switch
- Matched Rise and Fall
- Test & Measurement
- Data Synchronizers
- Data storage
- Guaranteed simultaneous switching noise level
- Set-reset capability
- Differential Individual
