74LVC821ADB,112
| Parameters | |
|---|---|
| Mounting Type | Surface Mount |
| Package / Case | 24-SSOP (0.209, 5.30mm Width) |
| Surface Mount | YES |
| Operating Temperature | -40°C~125°C TA |
| Packaging | Tube |
| Series | 74LVC |
| JESD-609 Code | e4 |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 24 |
| Type | D-Type |
| Terminal Finish | NICKEL PALLADIUM GOLD |
| Subcategory | FF/Latches |
| Technology | CMOS |
| Voltage - Supply | 1.65V~3.6V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 2.7V |
| Terminal Pitch | 0.65mm |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Base Part Number | 74LVC821 |
| JESD-30 Code | R-PDSO-G24 |
| Function | Standard |
| Qualification Status | Not Qualified |
| Output Type | Tri-State, Non-Inverted |
| Number of Elements | 1 |
| Supply Voltage-Max (Vsup) | 3.6V |
| Power Supplies | 3.3V |
| Load Capacitance | 50pF |
| Number of Ports | 2 |
| Clock Frequency | 200MHz |
| Family | LVC/LCX/Z |
| Current - Quiescent (Iq) | 10μA |
| Output Characteristics | 3-STATE |
| Current - Output High, Low | 24mA 24mA |
| Output Polarity | TRUE |
| Max I(ol) | 0.024 A |
| Number of Bits per Element | 10 |
| Max Propagation Delay @ V, Max CL | 7.3ns @ 3.3V, 50pF |
| Prop. Delay@Nom-Sup | 9.5 ns |
| Trigger Type | Positive Edge |
| Input Capacitance | 5pF |
| Height Seated (Max) | 2mm |
| Length | 8.2mm |
| Width | 5.3mm |
| RoHS Status | ROHS3 Compliant |
74LVC821ADB,112 Overview
The flip flop is packaged in 24-SSOP (0.209, 5.30mm Width). It is contained within the Tubepackage. It is configured with Tri-State, Non-Invertedas an output. It is configured with a trigger that uses Positive Edge. Surface Mountmounts this electrical part. A supply voltage of 1.65V~3.6V is required for operation. A temperature of -40°C~125°C TAis used in the operation. Logic flip flops of this type are classified as D-Type. It is a type of FPGA belonging to the 74LVC series. You should not exceed 200MHzin the output frequency of the device. D latch consists of 1 elements. As a result, it consumes 10μA quiescent current and is not affected by external forces. Currently, there are 24 terminations. Members of the 74LVC821family make up this object. The power supply voltage is 2.7V. There is 5pF input capacitance for this T flip flop. It belongs to the family of electronic devices known as LVC/LCX/Z. It is included in FF/Latches. It reaches the maximum supply voltage (Vsup) at 3.6V. There are 3.3V power supplies attached to it. The D flip flop is embedded with 2ports.
74LVC821ADB,112 Features
Tube package
74LVC series
3.3V power supplies
74LVC821ADB,112 Applications
There are a lot of NXP USA Inc. 74LVC821ADB,112 Flip Flops applications.
- Bounce elimination switch
- Test & Measurement
- Frequency Dividers
- Matched Rise and Fall
- Latch
- ESCC
- ESD performance
- Circuit Design
- Computing
- QML qualified product
