74LVC821ADB,118
| Parameters | |
|---|---|
| Mounting Type | Surface Mount |
| Package / Case | 24-SSOP (0.209, 5.30mm Width) |
| Surface Mount | YES |
| Operating Temperature | -40°C~125°C TA |
| Packaging | Tape & Reel (TR) |
| Series | 74LVC |
| JESD-609 Code | e4 |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 24 |
| Type | D-Type |
| Terminal Finish | NICKEL PALLADIUM GOLD |
| Subcategory | FF/Latches |
| Packing Method | TAPE AND REEL |
| Technology | CMOS |
| Voltage - Supply | 1.65V~3.6V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 2.7V |
| Terminal Pitch | 0.65mm |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Base Part Number | 74LVC821 |
| JESD-30 Code | R-PDSO-G24 |
| Function | Standard |
| Qualification Status | Not Qualified |
| Output Type | Tri-State, Non-Inverted |
| Number of Elements | 1 |
| Supply Voltage-Max (Vsup) | 3.6V |
| Power Supplies | 3.3V |
| Load Capacitance | 50pF |
| Number of Ports | 2 |
| Clock Frequency | 200MHz |
| Family | LVC/LCX/Z |
| Current - Quiescent (Iq) | 10μA |
| Output Characteristics | 3-STATE |
| Current - Output High, Low | 24mA 24mA |
| Output Polarity | TRUE |
| Max I(ol) | 0.024 A |
| Number of Bits per Element | 10 |
| Max Propagation Delay @ V, Max CL | 7.3ns @ 3.3V, 50pF |
| Prop. Delay@Nom-Sup | 9.5 ns |
| Trigger Type | Positive Edge |
| Input Capacitance | 5pF |
| Height Seated (Max) | 2mm |
| Length | 8.2mm |
| Width | 5.3mm |
| RoHS Status | ROHS3 Compliant |
74LVC821ADB,118 Overview
The flip flop is packaged in a case of 24-SSOP (0.209, 5.30mm Width). It is included in the package Tape & Reel (TR). It is configured with Tri-State, Non-Invertedas an output. This trigger uses the value Positive Edge. Surface Mountis in the way of this electric part. With a supply voltage of 1.65V~3.6V volts, it operates. -40°C~125°C TAis the operating temperature. It is an electronic flip flop with the type D-Type. JK flip flop is a part of the 74LVCseries of FPGAs. This D flip flop should not have a frequency greater than 200MHz. D latch consists of 1 elements. It consumes 10μA of quiescent A total of 24terminations have been recorded. D latch belongs to the 74LVC821 family. A voltage of 2.7V is used to power it. This T flip flop has a capacitance of 5pF farads at the input. Electronic devices of this type belong to the LVC/LCX/Zfamily. This device is part of the FF/Latchesbase part number family. In this case, the maximum supply voltage (Vsup) reaches 3.6V. Considering its reliability, this T flip flop is well suited for TAPE AND REEL. An electrical current of 3.3V volts is applied to it. There are 2 ports embedded in the flip flops.
74LVC821ADB,118 Features
Tape & Reel (TR) package
74LVC series
3.3V power supplies
74LVC821ADB,118 Applications
There are a lot of NXP USA Inc. 74LVC821ADB,118 Flip Flops applications.
- Instrumentation
- Control circuits
- Data transfer
- Buffered Clock
- Communications
- High Performance Logic for test systems
- Shift Registers
- Data Synchronizers
- Frequency division
- Guaranteed simultaneous switching noise level
