74LVC823APW,118
| Parameters | |
|---|---|
| Number of Pins | 24 |
| Operating Temperature | -40°C~125°C TA |
| Packaging | Tape & Reel (TR) |
| Series | 74LVC |
| JESD-609 Code | e4 |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 24 |
| Type | D-Type |
| Terminal Finish | Nickel/Palladium/Gold (Ni/Pd/Au) |
| Additional Feature | WITH CLEAR AND CLOCK ENABLE |
| Technology | CMOS |
| Voltage - Supply | 1.65V~3.6V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Supply Voltage | 1.8V |
| Terminal Pitch | 0.65mm |
| Base Part Number | 74LVC823 |
| Function | Master Reset |
| Output Type | Tri-State, Non-Inverted |
| Number of Elements | 1 |
| Polarity | Non-Inverting |
| Supply Voltage-Max (Vsup) | 3.6V |
| Number of Ports | 2 |
| Number of Bits | 9 |
| Clock Frequency | 200MHz |
| Propagation Delay | 5.1 ns |
| Turn On Delay Time | 3.7 ns |
| Family | LVC/LCX/Z |
| Logic Function | D-Type, Flip-Flop |
| Current - Quiescent (Iq) | 10μA |
| Output Characteristics | 3-STATE |
| Current - Output High, Low | 24mA 24mA |
| Max Propagation Delay @ V, Max CL | 10ns @ 3.3V, 50pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 5pF |
| Number of Input Lines | 9 |
| Clock Edge Trigger Type | Positive Edge |
| Length | 7.8mm |
| Width | 4.4mm |
| Radiation Hardening | No |
| RoHS Status | ROHS3 Compliant |
| Lead Free | Lead Free |
| Factory Lead Time | 1 Week |
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 24-TSSOP (0.173, 4.40mm Width) |
74LVC823APW,118 Overview
It is embeded in 24-TSSOP (0.173, 4.40mm Width) case. It is included in the package Tape & Reel (TR). It is configured with Tri-State, Non-Invertedas an output. This trigger is configured to use Positive Edge. Surface Mountmounts this electrical part. A voltage of 1.65V~3.6Vis required for its operation. In this case, the operating temperature is -40°C~125°C TA. This D latch has the type D-Type. In this case, it is a type of FPGA belonging to the 74LVC series. It should not exceed 200MHzin terms of its output frequency. In total, it contains 1 elements. As a result, it consumes 10μA quiescent current. There are 24 terminations, which are the practice of ending a transmission line with a device that matches the characteristic impedance of the line. Members of the 74LVC823family make up this object. It is powered by a voltage of 1.8V . A 5pFfarad input capacitance is provided by this T flip flop. The electronic device belongs to the LVC/LCX/Zfamily. This electronic part is mounted in the way of Surface Mount. It is designed with 24 pins. This device has the clock edge trigger type of Positive Edge. It is designed with a number of bits of 9. 3.6Vis the maximum supply voltage (Vsup). The D flip flop is embedded with 2ports. Currently, there are 9 input lines present. Furthermore, it has WITH CLEAR AND CLOCK ENABLEas a characteristic.
74LVC823APW,118 Features
Tape & Reel (TR) package
74LVC series
24 pins
9 Bits
74LVC823APW,118 Applications
There are a lot of Nexperia USA Inc. 74LVC823APW,118 Flip Flops applications.
- Bus hold
- Latch
- Data storage
- Modulo – n – counter
- Computers
- Frequency Dividers
- Count Modes
- Buffered Clock
- Power down protection
- Memory
