74LVT273BQ,115
| Parameters | |
|---|---|
| Mounting Type | Surface Mount |
| Package / Case | 20-VFQFN Exposed Pad |
| Surface Mount | YES |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Tape & Reel (TR) |
| Series | 74LVT |
| JESD-609 Code | e4 |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 20 |
| Type | D-Type |
| Terminal Finish | NICKEL PALLADIUM GOLD |
| Subcategory | FF/Latches |
| Packing Method | TAPE AND REEL |
| Technology | BICMOS |
| Voltage - Supply | 2.7V~3.6V |
| Terminal Position | QUAD |
| Terminal Form | NO LEAD |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 3.3V |
| Terminal Pitch | 0.5mm |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Base Part Number | 74LVT273 |
| JESD-30 Code | R-PQCC-N20 |
| Function | Master Reset |
| Qualification Status | Not Qualified |
| Output Type | Non-Inverted |
| Number of Elements | 1 |
| Supply Voltage-Max (Vsup) | 3.6V |
| Power Supplies | 3.3V |
| Supply Voltage-Min (Vsup) | 2.7V |
| Load Capacitance | 50pF |
| Clock Frequency | 150MHz |
| Family | LVT |
| Current - Quiescent (Iq) | 190μA |
| Current - Output High, Low | 32mA 64mA |
| Output Polarity | TRUE |
| Max I(ol) | 0.064 A |
| Number of Bits per Element | 8 |
| Max Propagation Delay @ V, Max CL | 5.5ns @ 3.3V, 50pF |
| Prop. Delay@Nom-Sup | 5.5 ns |
| Trigger Type | Positive Edge |
| Input Capacitance | 4pF |
| Propagation Delay (tpd) | 6.3 ns |
| Length | 4.5mm |
| Width | 2.5mm |
| RoHS Status | ROHS3 Compliant |
74LVT273BQ,115 Overview
20-VFQFN Exposed Padis the packaging method. There is an embedded version in the package Tape & Reel (TR). T flip flop uses Non-Invertedas the output. JK flip flop uses Positive Edgeas the trigger. In this case, the electronic component is mounted in the way of Surface Mount. The supply voltage is set to 2.7V~3.6V. It is operating at a temperature of -40°C~85°C TA. D-Typeis the type of this D latch. FPGAs belonging to the 74LVTseries contain this type of chip. A frequency of 150MHzshould be the maximum output frequency. A total of 1 elements are present. There is 190μA quiescent consumption. In 20terminations, a transmission line is terminated with a JK flip flop that matches its characteristic impedance. The object belongs to the 74LVT273 family. It is powered from a supply voltage of 3.3V. The input capacitance of this T flip flop is 4pF farads, which is defined as the capacitance between the input terminals of an op amp with either input grounded. Devices in the LVTfamily are electronic devices. It is included in FF/Latches. There is a 3.6Vmaximum supply voltage (Vsup). The supply voltage (Vsup) should be kept above 2.7V for normal operation. Considering the reliability of this T flip flop, it is well suited for TAPE AND REEL. The D latch operates on 3.3V volts.
74LVT273BQ,115 Features
Tape & Reel (TR) package
74LVT series
3.3V power supplies
74LVT273BQ,115 Applications
There are a lot of NXP USA Inc. 74LVT273BQ,115 Flip Flops applications.
- Parallel data storage
- Cold spare funcion
- 2 – Bit synchronous counter
- Functionally equivalent to the MC10/100EL29
- Data transfer
- Latch
- ESD performance
- Computers
- Supports Live Insertion
- Load Control
