74LVT374PW,112
| Parameters | |
|---|---|
| Mounting Type | Surface Mount |
| Package / Case | 20-TSSOP (0.173, 4.40mm Width) |
| Surface Mount | YES |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Tube |
| Series | 74LVT |
| JESD-609 Code | e4 |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 20 |
| Type | D-Type |
| Terminal Finish | NICKEL PALLADIUM GOLD |
| Subcategory | FF/Latches |
| Technology | BICMOS |
| Voltage - Supply | 2.7V~3.6V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 3.3V |
| Terminal Pitch | 0.65mm |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Base Part Number | 74LVT374 |
| JESD-30 Code | R-PDSO-G20 |
| Function | Standard |
| Qualification Status | Not Qualified |
| Output Type | Tri-State, Non-Inverted |
| Number of Elements | 1 |
| Supply Voltage-Max (Vsup) | 3.6V |
| Power Supplies | 3.3V |
| Supply Voltage-Min (Vsup) | 2.7V |
| Load Capacitance | 50pF |
| Number of Ports | 2 |
| Clock Frequency | 200MHz |
| Family | LVT |
| Current - Quiescent (Iq) | 190μA |
| Output Characteristics | 3-STATE |
| Current - Output High, Low | 32mA 64mA |
| Output Polarity | TRUE |
| Max I(ol) | 0.064 A |
| Number of Bits per Element | 8 |
| Max Propagation Delay @ V, Max CL | 5.2ns @ 3.3V, 50pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 4pF |
| Propagation Delay (tpd) | 5.5 ns |
| Length | 6.5mm |
| Width | 4.4mm |
| RoHS Status | ROHS3 Compliant |
74LVT374PW,112 Overview
The package is in the form of 20-TSSOP (0.173, 4.40mm Width). As part of the package Tube, it is embedded. The output it is configured with uses Tri-State, Non-Inverted. This trigger uses the value Positive Edge. Surface Mountis positioned in the way of this electronic part. It operates with a supply voltage of 2.7V~3.6V. It is at -40°C~85°C TAdegrees Celsius that the system is operating. This D latch has the type D-Type. In terms of FPGAs, it belongs to the 74LVT series. Its output frequency should not exceed 200MHz Hz. A total of 1elements are contained within it. There is 190μA quiescent consumption. A total of 20 terminations have been made. You can search similar parts based on 74LVT374. It is powered from a supply voltage of 3.3V. The input capacitance of this T flip flop is 4pF farads, which is defined as the capacitance between the input terminals of an op amp with either input grounded. It belongs to the family of electronic devices known as LVT. This RS flip flops is a part number FF/Latches. In this case, the maximum supply voltage (Vsup) reaches 3.6V. If you want to maintain normal operation, you should keep the supply voltage (Vsup) above 2.7V. A power supply of 3.3Vis required to operate it. This flip flop has a total of 2ports.
74LVT374PW,112 Features
Tube package
74LVT series
3.3V power supplies
74LVT374PW,112 Applications
There are a lot of NXP USA Inc. 74LVT374PW,112 Flip Flops applications.
- Guaranteed simultaneous switching noise level
- Balanced 24 mA output drivers
- Balanced Propagation Delays
- Counters
- Shift registers
- Reduced system switching noise
- CMOS Process
- Automotive
- Latch-up performance
- Data transfer
