74LVT374SJX
| Parameters | |
|---|---|
| Mounting Type | Surface Mount |
| Package / Case | 20-SOIC (0.209, 5.30mm Width) |
| Surface Mount | YES |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Tape & Reel (TR) |
| Series | 74LVT |
| JESD-609 Code | e3 |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 20 |
| Type | D-Type |
| Terminal Finish | Matte Tin (Sn) |
| Technology | BICMOS |
| Voltage - Supply | 2.7V~3.6V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 3.3V |
| Reach Compliance Code | compliant |
| Time@Peak Reflow Temperature-Max (s) | NOT SPECIFIED |
| Base Part Number | 74LVT374 |
| JESD-30 Code | R-PDSO-G20 |
| Function | Standard |
| Qualification Status | Not Qualified |
| Output Type | Tri-State, Non-Inverted |
| Number of Elements | 1 |
| Supply Voltage-Max (Vsup) | 3.6V |
| Supply Voltage-Min (Vsup) | 2.7V |
| Number of Ports | 2 |
| Clock Frequency | 160MHz |
| Family | LVT |
| Current - Quiescent (Iq) | 190μA |
| Output Characteristics | 3-STATE |
| Current - Output High, Low | 32mA 64mA |
| Output Polarity | TRUE |
| Number of Bits per Element | 8 |
| Max Propagation Delay @ V, Max CL | 4.9ns @ 3.3V, 50pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 3pF |
| Propagation Delay (tpd) | 5.2 ns |
| Width | 5.3mm |
| RoHS Status | RoHS Compliant |
74LVT374SJX Overview
The item is packaged in 20-SOIC (0.209, 5.30mm Width)cases. The package Tape & Reel (TR)contains it. There is a Tri-State, Non-Invertedoutput configured with it. JK flip flop uses Positive Edgeas the trigger. It is mounted in the way of Surface Mount. A supply voltage of 2.7V~3.6V is required for operation. It is operating at -40°C~85°C TA. A flip flop of this type is classified as a D-Type. The FPGA belongs to the 74LVT series. This D flip flop should not have a frequency greater than 160MHz. The element count is 1 . There is 190μA quiescent consumption. Terminations are 20. The 74LVT374family includes it. A voltage of 3.3V is used as the power supply for this D latch. The input capacitance of this JK flip flopis 3pF farads. LVTis the family of this D flip flop. In this case, the maximum supply voltage (Vsup) reaches 3.6V. For normal operation, the supply voltage (Vsup) should be kept above 2.7V. The flip flop contains 2ports.
74LVT374SJX Features
Tape & Reel (TR) package
74LVT series
74LVT374SJX Applications
There are a lot of ON Semiconductor 74LVT374SJX Flip Flops applications.
- Safety Clamp
- Dynamic threshold performance
- Shift Registers
- Communications
- CMOS Process
- Differential Individual
- Synchronous counter
- ATE
- Latch-up performance
- Test & Measurement
