74LVT74PW,112
| Parameters | |
|---|---|
| Mounting Type | Surface Mount |
| Package / Case | 14-TSSOP (0.173, 4.40mm Width) |
| Surface Mount | YES |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Tube |
| Series | 74LVT |
| JESD-609 Code | e4 |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 14 |
| Type | D-Type |
| Terminal Finish | NICKEL PALLADIUM GOLD |
| Subcategory | FF/Latches |
| Technology | BICMOS |
| Voltage - Supply | 2.7V~3.6V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 3.3V |
| Terminal Pitch | 0.65mm |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Base Part Number | 74LVT74 |
| Function | Set(Preset) and Reset |
| Qualification Status | Not Qualified |
| Output Type | Differential |
| Number of Elements | 2 |
| Supply Voltage-Max (Vsup) | 3.6V |
| Power Supplies | 3.3V |
| Load Capacitance | 50pF |
| Clock Frequency | 345MHz |
| Family | LVT |
| Current - Quiescent (Iq) | 1mA |
| Current - Output High, Low | 20mA 32mA |
| Output Polarity | COMPLEMENTARY |
| Number of Bits per Element | 1 |
| Max Propagation Delay @ V, Max CL | 5ns @ 3.3V, 50pF |
| Prop. Delay@Nom-Sup | 5 ns |
| Trigger Type | Positive Edge |
| Input Capacitance | 3pF |
| Propagation Delay (tpd) | 5 ns |
| Length | 5mm |
| Width | 4.4mm |
| RoHS Status | ROHS3 Compliant |
74LVT74PW,112 Overview
The flip flop is packaged in a case of 14-TSSOP (0.173, 4.40mm Width). There is an embedded version in the package Tube. Currently, the output is configured to use Differential. The trigger configured with it uses Positive Edge. There is an electronic component mounted in the way of Surface Mount. With a supply voltage of 2.7V~3.6V volts, it operates. Temperature is set to -40°C~85°C TA. It is an electronic flip flop with the type D-Type. In terms of FPGAs, it belongs to the 74LVT series. In order for it to function properly, its output frequency should not exceed 345MHz. There are 2 elements in it. During its operation, it consumes 1mA quiescent energy. The number of terminations is 14. The 74LVT74family includes it. An input voltage of 3.3Vpowers the D latch. This JK flip flop has a 3pFfarad input capacitance. It is a member of the LVTfamily of D flip flop. There is a base part number FF/Latchesfor the RS flip flops. As soon as 3.6Vis reached, Vsup reaches its maximum value. An electrical current of 3.3V volts is applied to it.
74LVT74PW,112 Features
Tube package
74LVT series
3.3V power supplies
74LVT74PW,112 Applications
There are a lot of NXP USA Inc. 74LVT74PW,112 Flip Flops applications.
- Frequency Dividers
- Shift registers
- Single Up Count-Control Line
- ATE
- ESD performance
- Frequency division
- Storage registers
- Asynchronous counter
- Shift Registers
- Supports Live Insertion
