74LVTH273SJ
| Parameters | |
|---|---|
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 3V |
| Reach Compliance Code | unknown |
| Time@Peak Reflow Temperature-Max (s) | NOT SPECIFIED |
| JESD-30 Code | R-PDSO-G20 |
| Function | Master Reset |
| Qualification Status | COMMERCIAL |
| Output Type | Non-Inverted |
| Number of Elements | 1 |
| Supply Voltage-Max (Vsup) | 3.6V |
| Supply Voltage-Min (Vsup) | 2.7V |
| Clock Frequency | 150MHz |
| Family | LVT |
| Current - Quiescent (Iq) | 190μA |
| Current - Output High, Low | 32mA 64mA |
| Output Polarity | TRUE |
| Number of Bits per Element | 8 |
| Max Propagation Delay @ V, Max CL | 4.9ns @ 3.3V, 50pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 3pF |
| Propagation Delay (tpd) | 5.5 ns |
| Width | 5.3mm |
| RoHS Status | ROHS3 Compliant |
| Mounting Type | Surface Mount |
| Package / Case | 20-SOIC (0.209, 5.30mm Width) |
| Surface Mount | YES |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Tube |
| Series | 74LVTH |
| JESD-609 Code | e3 |
| Pbfree Code | yes |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 20 |
| Type | D-Type |
| Terminal Finish | MATTE TIN |
| Technology | BICMOS |
| Voltage - Supply | 2.7V~3.6V |
| Terminal Position | DUAL |
74LVTH273SJ Overview
It is packaged in the way of 20-SOIC (0.209, 5.30mm Width). As part of the package Tube, it is embedded. As configured, the output uses Non-Inverted. JK flip flop uses Positive Edgeas the trigger. There is an electronic component mounted in the way of Surface Mount. A voltage of 2.7V~3.6Vis used as the supply voltage. In this case, the operating temperature is -40°C~85°C TA. This logic flip flop is classified as type D-Type. This type of FPGA is a part of the 74LVTH series. It should not exceed 150MHzin terms of its output frequency. In total, it contains 1 elements. T flip flop consumes 190μA quiescent energy. It has been determined that there have been 20 terminations. A voltage of 3V provides power to the D latch. The input capacitance of this T flip flop is 3pF farads, which is defined as the capacitance between the input terminals of an op amp with either input grounded. Electronic devices of this type belong to the LVTfamily. It reaches the maximum supply voltage (Vsup) at 3.6V. For normal operation, the supply voltage (Vsup) should be above 2.7V.
74LVTH273SJ Features
Tube package
74LVTH series
74LVTH273SJ Applications
There are a lot of Rochester Electronics, LLC 74LVTH273SJ Flip Flops applications.
- Computers
- Individual Asynchronous Resets
- Memory
- Functionally equivalent to the MC10/100EL29
- ESD protection
- Consumer
- Guaranteed simultaneous switching noise level
- ATE
- Modulo – n – counter
- Pattern generators
