74LVTH574PW,112
| Parameters | |
|---|---|
| Mounting Type | Surface Mount |
| Package / Case | 20-TSSOP (0.173, 4.40mm Width) |
| Surface Mount | YES |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Tube |
| Series | 74LVTH |
| JESD-609 Code | e4 |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 20 |
| Type | D-Type |
| Terminal Finish | Nickel/Palladium/Gold (Ni/Pd/Au) |
| Subcategory | FF/Latches |
| Technology | BICMOS |
| Voltage - Supply | 2.7V~3.6V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 3V |
| Terminal Pitch | 0.65mm |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Base Part Number | 74LVTH574 |
| JESD-30 Code | R-PDSO-G20 |
| Function | Standard |
| Qualification Status | Not Qualified |
| Output Type | Tri-State, Non-Inverted |
| Number of Elements | 1 |
| Supply Voltage-Max (Vsup) | 3.6V |
| Power Supplies | 3.3V |
| Supply Voltage-Min (Vsup) | 2.7V |
| Load Capacitance | 50pF |
| Number of Ports | 2 |
| Clock Frequency | 150MHz |
| Family | LVT |
| Current - Quiescent (Iq) | 190μA |
| Output Characteristics | 3-STATE |
| Current - Output High, Low | 32mA 64mA |
| Output Polarity | TRUE |
| Max I(ol) | 0.064 A |
| Number of Bits per Element | 8 |
| Max Propagation Delay @ V, Max CL | 5.9ns @ 3.3V, 50pF |
| Prop. Delay@Nom-Sup | 5.9 ns |
| Trigger Type | Positive Edge |
| Input Capacitance | 4pF |
| Propagation Delay (tpd) | 6.6 ns |
| Length | 6.5mm |
| Width | 4.4mm |
| RoHS Status | ROHS3 Compliant |
74LVTH574PW,112 Overview
It is packaged in the way of 20-TSSOP (0.173, 4.40mm Width). The Tubepackage contains it. T flip flop is configured with an output of Tri-State, Non-Inverted. This trigger uses the value Positive Edge. In this case, the electronic component is mounted in the way of Surface Mount. A 2.7V~3.6Vsupply voltage is required for it to operate. In the operating environment, the temperature is -40°C~85°C TA. It belongs to the type D-Typeof flip flops. It is a type of FPGA belonging to the 74LVTH series. Its output frequency should not exceed 150MHz. A total of 1elements are present in it. Despite external influences, it consumes 190μAof quiescent current. There have been 20 terminations. If you search by 74LVTH574, you will find similar parts. An input voltage of 3Vpowers the D latch. This JK flip flop has a 4pFfarad input capacitance. In terms of electronic devices, this device belongs to the LVTfamily of devices. This device is part of the FF/Latchesbase part number family. There is a 3.6Vmaximum supply voltage (Vsup). For normal operation, the supply voltage (Vsup) should be above 2.7V. There are 3.3V power supplies attached to it. This flip flop has a total of 2ports.
74LVTH574PW,112 Features
Tube package
74LVTH series
3.3V power supplies
74LVTH574PW,112 Applications
There are a lot of NXP USA Inc. 74LVTH574PW,112 Flip Flops applications.
- Individual Asynchronous Resets
- Data transfer
- Parallel data storage
- ESD performance
- Reduced system switching noise
- Frequency Dividers
- Modulo – n – counter
- Automotive
- Dynamic threshold performance
- Single Up Count-Control Line
