74V1G79STR
| Parameters | |
|---|---|
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | SC-74A, SOT-753 |
| Number of Pins | 5 |
| Operating Temperature | -55°C~125°C TA |
| Packaging | Tape & Reel (TR) |
| Series | 74V |
| JESD-609 Code | e3 |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 5 |
| Termination | SMD/SMT |
| Type | D-Type |
| Terminal Finish | Matte Tin (Sn) - annealed |
| Subcategory | FF/Latches |
| Technology | CMOS |
| Voltage - Supply | 2V~5.5V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | NOT SPECIFIED |
| Supply Voltage | 3.3V |
| Reach Compliance Code | unknown |
| Time@Peak Reflow Temperature-Max (s) | NOT SPECIFIED |
| Base Part Number | 74V1G79 |
| Function | Standard |
| Qualification Status | Not Qualified |
| Output Type | Non-Inverted |
| Polarity | Non-Inverting |
| Supply Voltage-Min (Vsup) | 2V |
| Number of Circuits | 1 |
| Output Current | 8mA |
| Number of Bits | 1 |
| Clock Frequency | 180MHz |
| Propagation Delay | 8.5 ns |
| Turn On Delay Time | 4.5 ns |
| Family | 74V |
| Logic Function | D-Type, Flip-Flop |
| Current - Quiescent (Iq) | 1μA |
| Current - Output High, Low | 8mA 8mA |
| Max I(ol) | 0.004 A |
| Max Propagation Delay @ V, Max CL | 6.5ns @ 5V, 50pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 4pF |
| Clock Edge Trigger Type | Positive Edge |
| Length | 2.9mm |
| REACH SVHC | No SVHC |
| RoHS Status | ROHS3 Compliant |
| Lead Free | Lead Free |
74V1G79STR Overview
The item is packaged in SC-74A, SOT-753cases. Package Tape & Reel (TR)embeds it. T flip flop is configured with an output of Non-Inverted. This trigger is configured to use Positive Edge. Surface Mountis positioned in the way of this electronic part. It operates with a supply voltage of 2V~5.5V. In this case, the operating temperature is -55°C~125°C TA. This electronic flip flop is of type D-Type. In this case, it is a type of FPGA belonging to the 74V series. It should not exceed 180MHzin its output frequency. During its operation, it consumes 1μA quiescent energy. There have been 5 terminations. D latch belongs to the 74V1G79 family. A voltage of 3.3V is used to power it. JK flip flop input capacitance is 4pF farads. In terms of electronic devices, this device belongs to the 74Vfamily of devices. It is mounted in the way of Surface Mount. Basically, it is designed with a set of 5 pins. A Positive Edgeclock edge trigger is used in this device. The part you are looking for is included in FF/Latches. It is designed with a number of bits of 1. Normally, the supply voltage (Vsup) should be kept above 2V. The superior flexibility of this product is achieved by using 1 circuits. It offers maximum design flexibility with its output current of 8mA.
74V1G79STR Features
Tape & Reel (TR) package
74V series
5 pins
1 Bits
74V1G79STR Applications
There are a lot of STMicroelectronics 74V1G79STR Flip Flops applications.
- Cold spare funcion
- ESCC
- Clock pulse
- Differential Individual
- Registers
- Test & Measurement
- QML qualified product
- Memory
- Single Down Count-Control Line
- Control circuits
