74V1G80STR
| Parameters | |
|---|---|
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | SC-74A, SOT-753 |
| Number of Pins | 5 |
| Operating Temperature | -55°C~125°C TA |
| Packaging | Tape & Reel (TR) |
| Series | 74V |
| JESD-609 Code | e3 |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 5 |
| Type | D-Type |
| Terminal Finish | Matte Tin (Sn) - annealed |
| Subcategory | FF/Latches |
| Packing Method | TAPE AND REEL |
| Technology | CMOS |
| Voltage - Supply | 2V~5.5V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | NOT SPECIFIED |
| Supply Voltage | 3.3V |
| Time@Peak Reflow Temperature-Max (s) | NOT SPECIFIED |
| Base Part Number | 74V1G80 |
| Function | Standard |
| Qualification Status | Not Qualified |
| Output Type | Inverted |
| Polarity | Inverting |
| Supply Voltage-Min (Vsup) | 2V |
| Number of Circuits | 1 |
| Number of Bits | 1 |
| Clock Frequency | 180MHz |
| Propagation Delay | 12 ns |
| Turn On Delay Time | 4.5 ns |
| Family | 74V |
| Logic Function | D-Type, Flip-Flop |
| Current - Quiescent (Iq) | 1μA |
| Current - Output High, Low | 8mA 8mA |
| Max I(ol) | 0.004 A |
| Max Propagation Delay @ V, Max CL | 8ns @ 5V, 50pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 4pF |
| Clock Edge Trigger Type | Positive Edge |
| Length | 2.9mm |
| RoHS Status | ROHS3 Compliant |
| Lead Free | Lead Free |
74V1G80STR Overview
SC-74A, SOT-753is the packaging method. As part of the package Tape & Reel (TR), it is embedded. Currently, the output is configured to use Inverted. It is configured with a trigger that uses Positive Edge. Surface Mountis positioned in the way of this electronic part. Powered by a 2V~5.5Vvolt supply, it operates as follows. It is operating at -55°C~125°C TA. The type of this D latch is D-Type. This type of FPGA is a part of the 74V series. It should not exceed 180MHzin its output frequency. During its operation, it consumes 1μA quiescent energy. 5terminations have occurred. You can search similar parts based on 74V1G80. An input voltage of 3.3Vpowers the D latch. The input capacitance of this T flip flop is 4pF farads, which is defined as the capacitance between the input terminals of an op amp with either input grounded. It is a member of the 74Vfamily of D flip flop. It is mounted in the way of Surface Mount. It is designed with 5 pins. It has a clock edge trigger type of Positive Edge. It is included in FF/Latches. An electronic part designed with 1bits is used in this application. For normal operation, the supply voltage (Vsup) should be kept above 2V. Its superior flexibility is attributed to its use of 1 circuits. In light of its reliable performance, this T flip flop is well suited for TAPE AND REEL.
74V1G80STR Features
Tape & Reel (TR) package
74V series
5 pins
1 Bits
74V1G80STR Applications
There are a lot of STMicroelectronics 74V1G80STR Flip Flops applications.
- Memory
- Balanced Propagation Delays
- Common Clocks
- Storage registers
- CMOS Process
- Latch-up performance
- Storage Registers
- Latch
- Automotive
- Data transfer
