74VHC9273FT
| Parameters | |
|---|---|
| Factory Lead Time | 1 Week |
| Mounting Type | Surface Mount |
| Package / Case | 20-TSSOP (0.173, 4.40mm Width) |
| Surface Mount | YES |
| Operating Temperature | -40°C~125°C TA |
| Packaging | Tape & Reel (TR) |
| Series | 74VHC |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 20 |
| Type | D-Type |
| Technology | CMOS |
| Voltage - Supply | 2V~5.5V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | NOT SPECIFIED |
| Supply Voltage | 5V |
| Terminal Pitch | 0.65mm |
| Time@Peak Reflow Temperature-Max (s) | NOT SPECIFIED |
| JESD-30 Code | R-PDSO-G20 |
| Function | Master Reset |
| Output Type | Non-Inverted |
| Number of Elements | 1 |
| Supply Voltage-Max (Vsup) | 5.5V |
| Supply Voltage-Min (Vsup) | 2V |
| Clock Frequency | 100MHz |
| Family | AHC/VHC/H/U/V |
| Current - Quiescent (Iq) | 4μA |
| Current - Output High, Low | 8mA 8mA |
| Output Polarity | TRUE |
| Number of Bits per Element | 8 |
| Max Propagation Delay @ V, Max CL | 12.1ns @ 5V, 50pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 4pF |
| Propagation Delay (tpd) | 20.9 ns |
| Length | 6.5mm |
| Width | 4.4mm |
| RoHS Status | RoHS Compliant |
74VHC9273FT Overview
20-TSSOP (0.173, 4.40mm Width)is the way it is packaged. There is an embedded version in the package Tape & Reel (TR). Currently, the output is configured to use Non-Inverted. JK flip flop uses Positive Edgeas the trigger. There is an electrical part that is mounted in the way of Surface Mount. Powered by a 2V~5.5Vvolt supply, it operates as follows. It is at -40°C~125°C TAdegrees Celsius that the system is operating. It is an electronic flip flop with the type D-Type. The FPGA belongs to the 74VHC series. It should not exceed 100MHzin its output frequency. In total, it contains 1 elements. Despite external influences, it consumes 4μAof quiescent current. A total of 20 terminations have been made. A voltage of 5V is used to power it. The input capacitance of this T flip flop is 4pF farads, which is defined as the capacitance between the input terminals of an op amp with either input grounded. The electronic device belongs to the AHC/VHC/H/U/Vfamily. As soon as Vsup reaches 5.5V, the maximum supply voltage is reached. For normal operation, the supply voltage (Vsup) should be above 2V.
74VHC9273FT Features
Tape & Reel (TR) package
74VHC series
74VHC9273FT Applications
There are a lot of Toshiba Semiconductor and Storage 74VHC9273FT Flip Flops applications.
- Control circuits
- QML qualified product
- Data Synchronizers
- Test & Measurement
- Single Up Count-Control Line
- Functionally equivalent to the MC10/100EL29
- Differential Individual
- Communications
- Count Modes
- ESD protection
