CD74HC107E
| Parameters | |
|---|---|
| Number of Channels | 2 |
| Load Capacitance | 50pF |
| Output Current | 5.2mA |
| Clock Frequency | 60MHz |
| Propagation Delay | 170 ns |
| Quiescent Current | 4μA |
| Turn On Delay Time | 14 ns |
| Family | HC/UH |
| Logic Function | Flip-Flop, JK-Type |
| Current - Output High, Low | 5.2mA 5.2mA |
| Max I(ol) | 0.006 A |
| Number of Bits per Element | 1 |
| Max Propagation Delay @ V, Max CL | 29ns @ 6V, 50pF |
| Trigger Type | Negative Edge |
| Input Capacitance | 10pF |
| Power Supply Current-Max (ICC) | 0.04mA |
| Clock Edge Trigger Type | Negative Edge |
| Height | 5.08mm |
| Length | 19.3mm |
| Width | 6.35mm |
| Thickness | 3.9mm |
| Radiation Hardening | No |
| REACH SVHC | No SVHC |
| RoHS Status | ROHS3 Compliant |
| Lead Free | Lead Free |
| Factory Lead Time | 1 Week |
| Lifecycle Status | ACTIVE (Last Updated: 4 days ago) |
| Contact Plating | Gold |
| Mount | Through Hole |
| Mounting Type | Through Hole |
| Package / Case | 14-DIP (0.300, 7.62mm) |
| Number of Pins | 14 |
| Weight | 927.99329mg |
| Operating Temperature | -55°C~125°C TA |
| Packaging | Tube |
| Series | 74HC |
| JESD-609 Code | e4 |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 14 |
| Type | JK Type |
| Subcategory | FF/Latches |
| Technology | CMOS |
| Voltage - Supply | 2V~6V |
| Terminal Position | DUAL |
| Supply Voltage | 4.5V |
| Base Part Number | 74HC107 |
| Function | Reset |
| Output Type | Differential |
| Polarity | Non-Inverting |
| Supply Voltage-Max (Vsup) | 6V |
| Supply Voltage-Min (Vsup) | 2V |
CD74HC107E Overview
14-DIP (0.300, 7.62mm)is the way it is packaged. As part of the package Tube, it is embedded. There is a Differentialoutput configured with it. This trigger is configured to use Negative Edge. There is an electric part mounted in the way of Through Hole. With a supply voltage of 2V~6V volts, it operates. Currently, the operating temperature is -55°C~125°C TA. JK Typeis the type of this D latch. It belongs to the 74HCseries of FPGAs. This D flip flop should not have a frequency greater than 60MHz. A total of 14terminations have been recorded. This D latch belongs to the family of 74HC107. The D flip flop is powered by a voltage of 4.5V . There is 10pF input capacitance for this T flip flop. Devices in the HC/UHfamily are electronic devices. There is an electronic component mounted in the way of Through Hole. 14pins are included in its design. This device has the clock edge trigger type of Negative Edge. The part you are looking for is included in FF/Latches. 6Vis the maximum supply voltage (Vsup). Normally, the supply voltage (Vsup) should be above 2V. In addition to its maximum design flexibility, the output current of the T flip flop is 5.2mA. Despite external influences, it consumes 4μAof quiescent current. The number of channels is growing strong/weak: 2.
CD74HC107E Features
Tube package
74HC series
14 pins
CD74HC107E Applications
There are a lot of Texas Instruments CD74HC107E Flip Flops applications.
- Frequency Dividers
- Memory
- Common Clocks
- Bus hold
- Individual Asynchronous Resets
- Frequency division
- Power down protection
- ESD performance
- Instrumentation
- Communications
