CD74HC107EG4
| Parameters | |
|---|---|
| Factory Lead Time | 1 Week |
| Mounting Type | Through Hole |
| Package / Case | 14-DIP (0.300, 7.62mm) |
| Supplier Device Package | 14-PDIP |
| Operating Temperature | -55°C~125°C TA |
| Packaging | Tube |
| Series | 74HC |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Type | JK Type |
| Voltage - Supply | 2V~6V |
| Base Part Number | 74HC107 |
| Function | Reset |
| Output Type | Differential |
| Number of Elements | 2 |
| Clock Frequency | 60MHz |
| Current - Quiescent (Iq) | 4μA |
| Current - Output High, Low | 5.2mA 5.2mA |
| Number of Bits per Element | 1 |
| Max Propagation Delay @ V, Max CL | 29ns @ 6V, 50pF |
| Trigger Type | Negative Edge |
| Input Capacitance | 10pF |
| RoHS Status | ROHS3 Compliant |
CD74HC107EG4 Overview
14-DIP (0.300, 7.62mm)is the packaging method. You can find it in the Tubepackage. This output is configured with Differential. It is configured with the trigger Negative Edge. Through Holeis occupied by this electronic component. A voltage of 2V~6Vis used as the supply voltage. A temperature of -55°C~125°C TAis considered to be the operating temperature. JK Typeis the type of this D latch. It belongs to the 74HCseries of FPGAs. It should not exceed 60MHzin its output frequency. D latch consists of 2 elements. There is 4μA quiescent consumption. The 74HC107 family contains this object. JK flip flop input capacitance is 10pF farads.
CD74HC107EG4 Features
Tube package
74HC series
CD74HC107EG4 Applications
There are a lot of Texas Instruments CD74HC107EG4 Flip Flops applications.
- Divide a clock signal by 2 or 4
- Parallel data storage
- Guaranteed simultaneous switching noise level
- Frequency Dividers
- Matched Rise and Fall
- Patented noise
- Frequency division
- Automotive
- High Performance Logic for test systems
- CMOS Process
