CD74HC112PWT
| Parameters | |
|---|---|
| Factory Lead Time | 1 Week |
| Lifecycle Status | ACTIVE (Last Updated: 2 days ago) |
| Contact Plating | Gold |
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 16-TSSOP (0.173, 4.40mm Width) |
| Number of Pins | 16 |
| Weight | 61.887009mg |
| Operating Temperature | -55°C~125°C TA |
| Packaging | Tape & Reel (TR) |
| Series | 74HC |
| JESD-609 Code | e4 |
| Pbfree Code | yes |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 16 |
| Termination | SMD/SMT |
| Type | JK Type |
| Subcategory | FF/Latches |
| Packing Method | TR |
| Technology | CMOS |
| Voltage - Supply | 2V~6V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 4.5V |
| Time@Peak Reflow Temperature-Max (s) | NOT SPECIFIED |
| Base Part Number | 74HC112 |
| Function | Set(Preset) and Reset |
| Qualification Status | Not Qualified |
| Output Type | Differential |
| Polarity | Non-Inverting |
| Supply Voltage-Max (Vsup) | 6V |
| Supply Voltage-Min (Vsup) | 2V |
| Number of Circuits | 2 |
| Load Capacitance | 50pF |
| Output Current | 5.2mA |
| Clock Frequency | 60MHz |
| Propagation Delay | 175 ns |
| Quiescent Current | 4μA |
| Turn On Delay Time | 14 ns |
| Family | HC/UH |
| Logic Function | AND, Flip-Flop, JK-Type |
| Current - Output High, Low | 5.2mA 5.2mA |
| Max I(ol) | 0.006 A |
| Number of Bits per Element | 1 |
| Max Propagation Delay @ V, Max CL | 30ns @ 6V, 50pF |
| Prop. Delay@Nom-Sup | 53 ns |
| Trigger Type | Negative Edge |
| Input Capacitance | 10pF |
| Schmitt Trigger | No |
| Power Supply Current-Max (ICC) | 0.04mA |
| Clock Edge Trigger Type | Negative Edge |
| Height | 1.2mm |
| Length | 5mm |
| Width | 4.4mm |
| Thickness | 1mm |
| REACH SVHC | No SVHC |
| RoHS Status | ROHS3 Compliant |
| Lead Free | Lead Free |
CD74HC112PWT Overview
The item is packaged in 16-TSSOP (0.173, 4.40mm Width)cases. A package named Tape & Reel (TR)includes it. Differentialis the output configured for it. Negative Edgeis the trigger it is configured with. The electronic part is mounted in the way of Surface Mount. A supply voltage of 2V~6V is required for operation. A temperature of -55°C~125°C TAis used in the operation. It belongs to the type JK Typeof flip flops. In FPGA terms, D flip flop is a type of 74HCseries FPGA. It should not exceed 60MHzin terms of its output frequency. The number of terminations is 16. JK flip flop belongs to 74HC112 family. An input voltage of 4.5Vpowers the D latch. The input capacitance of this JK flip flopis 10pF farads. In terms of electronic devices, this device belongs to the HC/UHfamily of devices. In this case, the electronic component is mounted in the way of Surface Mount. The electronic flip flop is designed with pins 16. This device has the clock edge trigger type of Negative Edge. This device has the base part number FF/Latches. Vsup reaches its maximum value at 6V. Keeping the supply voltage (Vsup) above 2V is necessary for normal operation. 2 circuits are used to achieve its superior flexibility. This D flip flop is well suited for TR based on its reliable performance. It offers maximum design flexibility with its output current of 5.2mA. In terms of quiescent current, it consumes 4μA .
CD74HC112PWT Features
Tape & Reel (TR) package
74HC series
16 pins
CD74HC112PWT Applications
There are a lot of Texas Instruments CD74HC112PWT Flip Flops applications.
- Event Detectors
- Data Synchronizers
- ESD protection
- Storage Registers
- Shift registers
- Convert a momentary switch to a toggle switch
- Single Down Count-Control Line
- Shift Registers
- Buffered Clock
- ATE
