MC100E431FNR2
| Parameters | |
|---|---|
| Function | Set(Preset) and Reset |
| Qualification Status | Not Qualified |
| Output Type | Differential |
| Polarity | Non-Inverting |
| Supply Voltage-Max (Vsup) | 5.7V |
| Power Supplies | -4.5V |
| Supply Voltage-Min (Vsup) | 4.2V |
| Number of Circuits | 3 |
| Clock Frequency | 1.1GHz |
| Propagation Delay | 850 ps |
| Turn On Delay Time | 700 ps |
| Logic Function | AND, Flip-Flop |
| Current - Quiescent (Iq) | 132mA |
| Output Characteristics | OPEN-EMITTER |
| Number of Bits per Element | 1 |
| Trigger Type | Positive, Negative |
| High Level Output Current | 50mA |
| Low Level Output Current | 50mA |
| Clock Edge Trigger Type | Positive Edge |
| Height Seated (Max) | 4.57mm |
| RoHS Status | Non-RoHS Compliant |
| Lead Free | Contains Lead |
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 28-LCC (J-Lead) |
| Number of Pins | 28 |
| Operating Temperature | 0°C~85°C TA |
| Packaging | Tape & Reel (TR) |
| Published | 2006 |
| Series | 100E |
| JESD-609 Code | e0 |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 3 (168 Hours) |
| Number of Terminations | 28 |
| Type | D-Type |
| Terminal Finish | Tin/Lead (Sn/Pb) |
| Additional Feature | NECL MODE: VCC = 0V WITH VEE = -4.2V TO -5.7V |
| Subcategory | FF/Latches |
| Packing Method | TAPE AND REEL |
| Technology | ECL |
| Voltage - Supply | -4.2V~-5.7V |
| Terminal Position | QUAD |
| Terminal Form | J BEND |
| Peak Reflow Temperature (Cel) | 240 |
| Supply Voltage | 5V |
| Reach Compliance Code | not_compliant |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Base Part Number | 100E431 |
MC100E431FNR2 Overview
The item is packaged in 28-LCC (J-Lead)cases. D flip flop is included in the Tape & Reel (TR)package. The output it is configured with uses Differential. In the configuration of the trigger, Positive, Negativeis used. In this case, the electronic component is mounted in the way of Surface Mount. The JK flip flop operates at -4.2V~-5.7Vvolts. It is operating at a temperature of 0°C~85°C TA. This D latch has the type D-Type. In this case, it is a type of FPGA belonging to the 100E series. Its output frequency should not exceed 1.1GHz Hz. As a result, it consumes 132mA of quiescent current without being affected by external factors. There have been 28 terminations. Members of the 100E431family make up this object. An input voltage of 5Vpowers the D latch. There is an electronic component mounted in the way of Surface Mount. There are 28pins on it. In this device, the clock edge trigger type is Positive Edge. It is included in FF/Latches. 5.7Vis the maximum supply voltage (Vsup). If you want to maintain normal operation, you should keep the supply voltage (Vsup) above 4.2V. Using 3 circuits, it is highly flexible. Considering its reliability, this T flip flop is well suited for TAPE AND REEL. A total of -4.5V power supplies are needed to run it. There is also a characteristic of NECL MODE: VCC = 0V WITH VEE = -4.2V TO -5.7V. High level output current is set to 50mA. It is set to 50mAfor low level output current.
MC100E431FNR2 Features
Tape & Reel (TR) package
100E series
28 pins
-4.5V power supplies
MC100E431FNR2 Applications
There are a lot of ON Semiconductor MC100E431FNR2 Flip Flops applications.
- Bus hold
- Test & Measurement
- Latch-up performance
- Balanced Propagation Delays
- Buffered Clock
- Registers
- Clock pulse
- Supports Live Insertion
- Convert a momentary switch to a toggle switch
- QML qualified product
