MC100E431FNR2G
| Parameters | |
|---|---|
| Mounting Type | Surface Mount |
| Package / Case | 28-LCC (J-Lead) |
| Surface Mount | YES |
| Operating Temperature | 0°C~85°C TA |
| Packaging | Tape & Reel (TR) |
| Series | 100E |
| JESD-609 Code | e3 |
| Pbfree Code | no |
| Part Status | Last Time Buy |
| Moisture Sensitivity Level (MSL) | 3 (168 Hours) |
| Number of Terminations | 28 |
| Type | D-Type |
| Terminal Finish | MATTE TIN |
| Additional Feature | NECL MODE: VCC = 0V WITH VEE = -4.2V TO -5.7V |
| Technology | ECL |
| Voltage - Supply | -4.2V~-5.7V |
| Terminal Position | QUAD |
| Terminal Form | J BEND |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 5V |
| Reach Compliance Code | unknown |
| Time@Peak Reflow Temperature-Max (s) | 40 |
| JESD-30 Code | S-PQCC-J28 |
| Function | Set(Preset) and Reset |
| Qualification Status | COMMERCIAL |
| Output Type | Differential |
| Number of Elements | 3 |
| Supply Voltage-Max (Vsup) | 5.7V |
| Supply Voltage-Min (Vsup) | 4.2V |
| Clock Frequency | 1.1GHz |
| Current - Quiescent (Iq) | 132mA |
| Output Characteristics | OPEN-EMITTER |
| Output Polarity | COMPLEMENTARY |
| Number of Bits per Element | 1 |
| Trigger Type | Positive, Negative |
| Propagation Delay (tpd) | 0.85 ns |
| Height Seated (Max) | 4.57mm |
| RoHS Status | ROHS3 Compliant |
MC100E431FNR2G Overview
It is packaged in the way of 28-LCC (J-Lead). It is included in the package Tape & Reel (TR). T flip flop uses Differentialas its output configuration. It is configured with a trigger that uses a value of Positive, Negative. It is mounted in the way of Surface Mount. The JK flip flop operates with an input voltage of -4.2V~-5.7V volts. 0°C~85°C TAis the operating temperature. A flip flop of this type is classified as a D-Type. FPGAs belonging to the 100Eseries contain this type of chip. A frequency of 1.1GHzshould not be exceeded by its output. The element count is 3 . There is a consumption of 132mAof quiescent energy. There are 28 terminations, which are the practice of ending a transmission line with a device that matches the characteristic impedance of the line. The power source is powered by 5V. In this case, the maximum supply voltage (Vsup) reaches 5.7V. A normal operating voltage (Vsup) should remain above 4.2V. As an additional reference, you may refer to electronic flip flop NECL MODE: VCC = 0V WITH VEE = -4.2V TO -5.7V.
MC100E431FNR2G Features
Tape & Reel (TR) package
100E series
MC100E431FNR2G Applications
There are a lot of Rochester Electronics, LLC MC100E431FNR2G Flip Flops applications.
- Data Synchronizers
- Registers
- Reduced system switching noise
- Control circuits
- ESCC
- Power down protection
- Storage Registers
- Communications
- Storage registers
- Individual Asynchronous Resets
