MC100EL35DR2
| Parameters | |
|---|---|
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 8-SOIC (0.154, 3.90mm Width) |
| Number of Pins | 8 |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Tape & Reel (TR) |
| Published | 2008 |
| Series | 100EL |
| JESD-609 Code | e0 |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 8 |
| Type | D-Type |
| Additional Feature | NECL MODE: VCC = 0V WITH VEE = -4.2V TO -5.7V |
| Subcategory | FF/Latches |
| Packing Method | TAPE AND REEL |
| Technology | ECL |
| Voltage - Supply | -4.2V~-5.7V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 240 |
| Supply Voltage | 5V |
| Reach Compliance Code | not_compliant |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Base Part Number | 100EL35 |
| Function | Reset |
| Qualification Status | Not Qualified |
| Output Type | Differential |
| Polarity | Non-Inverting |
| Supply Voltage-Max (Vsup) | 5.7V |
| Power Supplies | +-5V |
| Supply Voltage-Min (Vsup) | 4.2V |
| Number of Circuits | 1 |
| Number of Bits | 2 |
| Clock Frequency | 2.2GHz |
| Propagation Delay | 700 ps |
| Turn On Delay Time | 525 ps |
| Logic Function | Flip-Flop |
| Current - Quiescent (Iq) | 32mA |
| Output Characteristics | OPEN-EMITTER |
| Prop. Delay@Nom-Sup | 0.745 ns |
| Trigger Type | Positive Edge |
| Power Supply Current-Max (ICC) | 37mA |
| Clock Edge Trigger Type | Positive Edge |
| Length | 4.9mm |
| Width | 3.9mm |
| RoHS Status | Non-RoHS Compliant |
| Lead Free | Contains Lead |
MC100EL35DR2 Overview
It is embeded in 8-SOIC (0.154, 3.90mm Width) case. A package named Tape & Reel (TR)includes it. T flip flop uses Differentialas its output configuration. The trigger configured with it uses Positive Edge. In this case, the electronic component is mounted in the way of Surface Mount. A voltage of -4.2V~-5.7Vis required for its operation. In this case, the operating temperature is -40°C~85°C TA. This logic flip flop is classified as type D-Type. JK flip flop belongs to the 100ELseries of FPGAs. A frequency of 2.2GHzshould be the maximum output frequency. As a result, it consumes 32mA quiescent current and is not affected by external forces. Terminations are 8. D latch belongs to the 100EL35 family. Power is supplied from a voltage of 5V volts. Surface Mount mounts this electronic component. The 8pins are designed into the board. In this device, the clock edge trigger type is Positive Edge. The part you are looking for is included in FF/Latches. An electronic part designed with 2bits is used in this application. As soon as 5.7Vis reached, Vsup reaches its maximum value. It is imperative that the supply voltage (Vsup) is maintained above 4.2Vin order to ensure normal operation. To achieve this superior flexibility, 1 circuits are used. As a result of its reliability, this D flip flop is ideally suited for TAPE AND REEL. The D latch runs on a voltage of +-5V volts. Additionally, there are NECL MODE: VCC = 0V WITH VEE = -4.2V TO -5.7V on the electronic flip flop that can be referred to.
MC100EL35DR2 Features
Tape & Reel (TR) package
100EL series
8 pins
2 Bits
+-5V power supplies
MC100EL35DR2 Applications
There are a lot of ON Semiconductor MC100EL35DR2 Flip Flops applications.
- Frequency Divider circuits
- Buffer registers
- Instrumentation
- Data transfer
- High Performance Logic for test systems
- Matched Rise and Fall
- Control circuits
- QML qualified product
- Convert a momentary switch to a toggle switch
- Set-reset capability
