MC100EP35DR2
| Parameters | |
|---|---|
| Length | 4.9mm |
| Width | 3.9mm |
| RoHS Status | Non-RoHS Compliant |
| Mounting Type | Surface Mount |
| Package / Case | 8-SOIC (0.154, 3.90mm Width) |
| Surface Mount | YES |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Tape & Reel (TR) |
| Series | 100EP |
| JESD-609 Code | e0 |
| Pbfree Code | yes |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 8 |
| Type | JK Type |
| Terminal Finish | TIN LEAD |
| Additional Feature | NECL MODE: VCC = 0V WITH VEE = -3V TO -5.5V |
| Technology | ECL |
| Voltage - Supply | -3V~-5.5V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 240 |
| Supply Voltage | 3.3V |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| JESD-30 Code | R-PDSO-G8 |
| Function | Reset |
| Qualification Status | COMMERCIAL |
| Output Type | Differential |
| Number of Elements | 1 |
| Supply Voltage-Max (Vsup) | 5.5V |
| Supply Voltage-Min (Vsup) | 3V |
| Number of Bits | 2 |
| Clock Frequency | 3GHz |
| Current - Quiescent (Iq) | 50mA |
| Output Polarity | COMPLEMENTARY |
| Trigger Type | Positive Edge |
| Propagation Delay (tpd) | 0.49 ns |
MC100EP35DR2 Overview
The flip flop is packaged in a case of 8-SOIC (0.154, 3.90mm Width). A package named Tape & Reel (TR)includes it. T flip flop is configured with an output of Differential. This trigger uses the value Positive Edge. There is an electronic component mounted in the way of Surface Mount. A -3V~-5.5Vsupply voltage is required for it to operate. Currently, the operating temperature is -40°C~85°C TA. This D latch has the type JK Type. This type of FPGA is a part of the 100EP series. Its output frequency should not exceed 3GHz. In total, there are 1 elements. T flip flop consumes 50mA quiescent energy. A total of 8terminations have been recorded. An input voltage of 3.3Vpowers the D latch. It is designed with 2bits. Vsup reaches 5.5V, the maximal supply voltage. It is imperative that the supply voltage (Vsup) is maintained above 3Vin order to ensure normal operation. Additionally, you may refer to the D latch's additional NECL MODE: VCC = 0V WITH VEE = -3V TO -5.5V.
MC100EP35DR2 Features
Tape & Reel (TR) package
100EP series
2 Bits
MC100EP35DR2 Applications
There are a lot of Rochester Electronics, LLC MC100EP35DR2 Flip Flops applications.
- Functionally equivalent to the MC10/100EL29
- Single Down Count-Control Line
- Cold spare funcion
- Buffer registers
- Asynchronous counter
- Instrumentation
- Data transfer
- Communications
- CMOS Process
- EMI reduction circuitry
