MC100LVEL30DWR2G
| Parameters | |
|---|---|
| Factory Lead Time | 1 Week |
| Lifecycle Status | ACTIVE (Last Updated: 2 days ago) |
| Contact Plating | Tin |
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 20-SOIC (0.295, 7.50mm Width) |
| Number of Pins | 20 |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Tape & Reel (TR) |
| Published | 2006 |
| Series | 100LVEL |
| JESD-609 Code | e3 |
| Pbfree Code | yes |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 3 (168 Hours) |
| Number of Terminations | 20 |
| Type | D-Type |
| Subcategory | FF/Latches |
| Packing Method | TAPE AND REEL |
| Technology | ECL |
| Voltage - Supply | -3V~-3.8V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 3.3V |
| Time@Peak Reflow Temperature-Max (s) | 40 |
| Base Part Number | 100LVEL30 |
| Function | Set(Preset) and Reset |
| Output Type | Differential |
| Polarity | Non-Inverting |
| Supply Voltage-Min (Vsup) | 3V |
| Number of Circuits | 3 |
| Clock Frequency | 1.2GHz |
| Propagation Delay | 820 ps |
| Turn On Delay Time | 570 ps |
| Logic Function | AND, D-Type, Flip-Flop |
| Current - Quiescent (Iq) | 62mA |
| Output Characteristics | OPEN-EMITTER |
| Halogen Free | Halogen Free |
| Number of Bits per Element | 1 |
| Trigger Type | Positive Edge |
| Clock Edge Trigger Type | Positive Edge |
| Height Seated (Max) | 2.65mm |
| Width | 7.5mm |
| Radiation Hardening | No |
| RoHS Status | ROHS3 Compliant |
| Lead Free | Lead Free |
MC100LVEL30DWR2G Overview
20-SOIC (0.295, 7.50mm Width)is the packaging method. Package Tape & Reel (TR)embeds it. The output it is configured with uses Differential. It is configured with the trigger Positive Edge. Surface Mountis occupied by this electronic component. Powered by a -3V~-3.8Vvolt supply, it operates as follows. In the operating environment, the temperature is -40°C~85°C TA. This logic flip flop is classified as type D-Type. JK flip flop is a part of the 100LVELseries of FPGAs. In order for it to function properly, its output frequency should not exceed 1.2GHz. As a result, it consumes 62mA of quiescent current without being affected by external factors. 20terminations have occurred. JK flip flop belongs to 100LVEL30 family. Power is supplied from a voltage of 3.3V volts. This electronic part is mounted in the way of Surface Mount. With its 20pins, it is designed to work with most electronic flip flops. There is a clock edge trigger type of Positive Edgeon this device. The RS flip flops belongs to FF/Latches base part number. The supply voltage (Vsup) should be kept above 3V for normal operation. Its superior flexibility is attributed to its use of 3 circuits. Considering its reliability, this T flip flop is well suited for TAPE AND REEL.
MC100LVEL30DWR2G Features
Tape & Reel (TR) package
100LVEL series
20 pins
MC100LVEL30DWR2G Applications
There are a lot of ON Semiconductor MC100LVEL30DWR2G Flip Flops applications.
- Balanced Propagation Delays
- Supports Live Insertion
- Patented noise
- CMOS Process
- Cold spare funcion
- Computing
- Automotive
- 2 – Bit synchronous counter
- Data storage
- Frequency Dividers
