MC100LVEL31DTR2
| Parameters | |
|---|---|
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 8-TSSOP, 8-MSOP (0.118, 3.00mm Width) |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Tape & Reel (TR) |
| Published | 2008 |
| Series | 100LVEL |
| JESD-609 Code | e0 |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 3 (168 Hours) |
| Number of Terminations | 8 |
| Type | D-Type |
| Terminal Finish | Tin/Lead (Sn/Pb) |
| Additional Feature | NECL MODE: VCC = 0V WITH VEE = -3V TO -3.8V |
| Subcategory | FF/Latches |
| Packing Method | TAPE AND REEL |
| Technology | ECL |
| Voltage - Supply | -3V~-3.8V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 240 |
| Supply Voltage | 3.3V |
| Terminal Pitch | 0.65mm |
| Reach Compliance Code | not_compliant |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Base Part Number | 100LVEL31 |
| JESD-30 Code | S-PDSO-G8 |
| Function | Set(Preset) and Reset |
| Qualification Status | Not Qualified |
| Output Type | Differential |
| Polarity | Non-Inverting |
| Supply Voltage-Max (Vsup) | 3.8V |
| Power Supplies | -4.5V |
| Supply Voltage-Min (Vsup) | 3V |
| Number of Circuits | 1 |
| Number of Bits | 1 |
| Clock Frequency | 2.9GHz |
| Propagation Delay | 590 ps |
| Turn On Delay Time | 475 ps |
| Logic Function | AND, D-Type, Flip-Flop |
| Current - Quiescent (Iq) | 35mA |
| Trigger Type | Positive Edge |
| Power Supply Current-Max (ICC) | 38mA |
| fmax-Min | 2900 MHz |
| Clock Edge Trigger Type | Positive Edge |
| Max Frequency@Nom-Sup | 2900000000Hz |
| Length | 3mm |
| Width | 3mm |
| RoHS Status | Non-RoHS Compliant |
| Lead Free | Contains Lead |
MC100LVEL31DTR2 Overview
The flip flop is packaged in 8-TSSOP, 8-MSOP (0.118, 3.00mm Width). The package Tape & Reel (TR)contains it. The output it is configured with uses Differential. This trigger uses the value Positive Edge. It is mounted in the way of Surface Mount. A voltage of -3V~-3.8Vis used as the supply voltage. The operating temperature is -40°C~85°C TA. The type of this D latch is D-Type. In this case, it is a type of FPGA belonging to the 100LVEL series. A frequency of 2.9GHzshould be the maximum output frequency. During its operation, it consumes 35mA quiescent energy. There have been 8 terminations. JK flip flop belongs to 100LVEL31 family. A voltage of 3.3V is used to power it. Electronic part Surface Mountis mounted in the way. This device's clock edge trigger type is Positive Edge. The RS flip flops belongs to FF/Latches base part number. The design is based on 1bits. Vsup reaches its maximum value at 3.8V. A normal operating voltage (Vsup) should remain above 3V. The superior flexibility is achieved through the use of 1 circuits. Due to its reliability, this T flip flop is well suited for TAPE AND REEL. In order for the device to operate, it requires -4.5V power supplies. Additionally, you may refer to the additional NECL MODE: VCC = 0V WITH VEE = -3V TO -3.8V of the electronic flip flop.
MC100LVEL31DTR2 Features
Tape & Reel (TR) package
100LVEL series
1 Bits
-4.5V power supplies
MC100LVEL31DTR2 Applications
There are a lot of ON Semiconductor MC100LVEL31DTR2 Flip Flops applications.
- Patented noise
- Shift registers
- Buffered Clock
- Count Modes
- Single Up Count-Control Line
- Set-reset capability
- Memory
- Parallel data storage
- Latch-up performance
- Computers
