MC10E131FN
| Parameters | |
|---|---|
| Mounting Type | Surface Mount |
| Package / Case | 28-LCC (J-Lead) |
| Surface Mount | YES |
| Operating Temperature | 0°C~85°C TA |
| Packaging | Tube |
| Series | 10E |
| JESD-609 Code | e0 |
| Pbfree Code | yes |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 3 (168 Hours) |
| Number of Terminations | 28 |
| Type | D-Type |
| Terminal Finish | TIN LEAD |
| Technology | ECL |
| Voltage - Supply | -4.2V~-5.7V |
| Terminal Position | QUAD |
| Terminal Form | J BEND |
| Peak Reflow Temperature (Cel) | 240 |
| Supply Voltage | 5V |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| JESD-30 Code | S-PQCC-J28 |
| Function | Set(Preset) and Reset |
| Qualification Status | COMMERCIAL |
| Output Type | Differential |
| Number of Elements | 1 |
| Supply Voltage-Max (Vsup) | 5.7V |
| Clock Frequency | 1.4GHz |
| Family | 10E |
| Current - Quiescent (Iq) | 70mA |
| Output Characteristics | OPEN-EMITTER |
| Output Polarity | COMPLEMENTARY |
| Number of Bits per Element | 4 |
| Trigger Type | Positive Edge |
| Propagation Delay (tpd) | 0.675 ns |
| RoHS Status | Non-RoHS Compliant |
MC10E131FN Overview
28-LCC (J-Lead)is the way it is packaged. Package Tubeembeds it. This output is configured with Differential. In the configuration of the trigger, Positive Edgeis used. The electronic part is mounted in the way of Surface Mount. The JK flip flop operates at -4.2V~-5.7Vvolts. A temperature of 0°C~85°C TAis used in the operation. This electronic flip flop is of type D-Type. In terms of FPGAs, it belongs to the 10E series. You should not exceed 1.4GHzin its output frequency. In total, there are 1 elements. It consumes 70mA of quiescent The number of terminations is 28. The power source is powered by 5V. In this case, the D flip flop belongs to the 10Efamily. There is a 5.7Vmaximum supply voltage (Vsup).
MC10E131FN Features
Tube package
10E series
MC10E131FN Applications
There are a lot of Rochester Electronics, LLC MC10E131FN Flip Flops applications.
- Control circuits
- Computing
- High Performance Logic for test systems
- Matched Rise and Fall
- Parallel data storage
- Shift Registers
- Counters
- Digital electronics systems
- Buffer registers
- Set-reset capability
