Parameters |
Peak Reflow Temperature (Cel) |
240 |
Supply Voltage |
5V |
Terminal Pitch |
0.65mm |
Reach Compliance Code |
not_compliant |
Time@Peak Reflow Temperature-Max (s) |
30 |
Base Part Number |
10EL51 |
JESD-30 Code |
S-PDSO-G8 |
Function |
Reset |
Qualification Status |
Not Qualified |
Output Type |
Differential |
Polarity |
Non-Inverting |
Supply Voltage-Max (Vsup) |
5.7V |
Power Supplies |
-5.2V |
Supply Voltage-Min (Vsup) |
4.2V |
Number of Circuits |
1 |
Number of Bits |
1 |
Clock Frequency |
2.8GHz |
Propagation Delay |
565 ps |
Turn On Delay Time |
475 ps |
Logic Function |
Flip-Flop |
Current - Quiescent (Iq) |
29mA |
Prop. Delay@Nom-Sup |
0.62 ns |
Trigger Type |
Positive, Negative |
Power Supply Current-Max (ICC) |
29mA |
fmax-Min |
2200 MHz |
Clock Edge Trigger Type |
Positive Edge |
Max Frequency@Nom-Sup |
2200000000Hz |
Length |
3mm |
Width |
3mm |
RoHS Status |
Non-RoHS Compliant |
Lead Free |
Contains Lead |
Mount |
Surface Mount |
Mounting Type |
Surface Mount |
Package / Case |
8-TSSOP, 8-MSOP (0.118, 3.00mm Width) |
Operating Temperature |
-40°C~85°C TA |
Packaging |
Tape & Reel (TR) |
Published |
2008 |
Series |
10EL |
JESD-609 Code |
e0 |
Part Status |
Obsolete |
Moisture Sensitivity Level (MSL) |
3 (168 Hours) |
Number of Terminations |
8 |
Type |
D-Type |
Terminal Finish |
Tin/Lead (Sn/Pb) |
Additional Feature |
NECL MODE: VCC = 0V WITH VEE = -4.2V TO -5.7V |
Subcategory |
FF/Latches |
Packing Method |
TAPE AND REEL |
Technology |
ECL |
Voltage - Supply |
-4.2V~-5.7V |
Terminal Position |
DUAL |
Terminal Form |
GULL WING |
MC10EL51DTR2 Overview
As a result, it is packaged as 8-TSSOP, 8-MSOP (0.118, 3.00mm Width). As part of the package Tape & Reel (TR), it is embedded. The output it is configured with uses Differential. It is configured with the trigger Positive, Negative. Surface Mountis positioned in the way of this electronic part. The JK flip flop operates at a voltage of -4.2V~-5.7V. In the operating environment, the temperature is -40°C~85°C TA. This D latch has the type D-Type. In FPGA terms, D flip flop is a type of 10ELseries FPGA. You should not exceed 2.8GHzin its output frequency. It consumes 29mA of quiescent current without being affected by external factors. It has been determined that there have been 8 terminations. You can search similar parts based on 10EL51. A voltage of 5V is used to power it. There is an electronic part that is mounted in the way of Surface Mount. Its clock edge trigger type is Positive Edge. There is a base part number FF/Latchesfor the RS flip flops. This flip flop is designed with 1 Bits. It reaches the maximum supply voltage (Vsup) at 5.7V. The supply voltage (Vsup) should be maintained above 4.2V for normal operation. Using 1 circuits, it is highly flexible. Considering the reliability of this T flip flop, it is well suited for TAPE AND REEL. It operates from -5.2V power supplies. Additionally, you may refer to the D latch's additional NECL MODE: VCC = 0V WITH VEE = -4.2V TO -5.7V.
MC10EL51DTR2 Features
Tape & Reel (TR) package
10EL series
1 Bits
-5.2V power supplies
MC10EL51DTR2 Applications
There are a lot of ON Semiconductor MC10EL51DTR2 Flip Flops applications.
- ESCC
- Frequency Divider circuits
- Load Control
- Balanced Propagation Delays
- Synchronous counter
- Dynamic threshold performance
- Individual Asynchronous Resets
- Shift registers
- Frequency Dividers
- Automotive