MC10EP35DT
| Parameters | |
|---|---|
| Mounting Type | Surface Mount |
| Package / Case | 8-TSSOP, 8-MSOP (0.118, 3.00mm Width) |
| Surface Mount | YES |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Tube |
| Series | 10EP |
| JESD-609 Code | e0 |
| Pbfree Code | yes |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 8 |
| Type | JK Type |
| Terminal Finish | TIN LEAD |
| Additional Feature | NECL MODE: VCC = 0V WITH VEE = -3V TO -5.5V |
| Technology | ECL |
| Voltage - Supply | -3V~-5.5V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 240 |
| Supply Voltage | 3.3V |
| Terminal Pitch | 0.65mm |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| JESD-30 Code | S-PDSO-G8 |
| Function | Reset |
| Qualification Status | COMMERCIAL |
| Output Type | Differential |
| Number of Elements | 1 |
| Supply Voltage-Max (Vsup) | 5.5V |
| Supply Voltage-Min (Vsup) | 3V |
| Number of Bits | 2 |
| Clock Frequency | 3GHz |
| Family | 10E |
| Current - Quiescent (Iq) | 50mA |
| Output Polarity | COMPLEMENTARY |
| Trigger Type | Positive Edge |
| Propagation Delay (tpd) | 0.49 ns |
| Length | 3mm |
| Width | 3mm |
| RoHS Status | Non-RoHS Compliant |
MC10EP35DT Overview
It is packaged in the way of 8-TSSOP, 8-MSOP (0.118, 3.00mm Width). The package Tubecontains it. The output it is configured with uses Differential. The trigger configured with it uses Positive Edge. The electronic part is mounted in the way of Surface Mount. The JK flip flop operates at a voltage of -3V~-5.5V. It is operating at a temperature of -40°C~85°C TA. A flip flop of this type is classified as a JK Type. This type of FPGA is a part of the 10EP series. Its output frequency should not exceed 3GHz. A total of 1elements are present in it. Despite external influences, it consumes 50mAof quiescent current. Terminations are 8. Power is supplied from a voltage of 3.3V volts. Devices in the 10Efamily are electronic devices. The flip flop is designed with 2bits. In this case, the maximum supply voltage (Vsup) reaches 5.5V. For normal operation, the supply voltage (Vsup) should be above 3V. Additionally, you may refer to the D latch's additional NECL MODE: VCC = 0V WITH VEE = -3V TO -5.5V.
MC10EP35DT Features
Tube package
10EP series
2 Bits
MC10EP35DT Applications
There are a lot of Rochester Electronics, LLC MC10EP35DT Flip Flops applications.
- Data storage
- CMOS Process
- Safety Clamp
- High Performance Logic for test systems
- Buffered Clock
- Test & Measurement
- EMI reduction circuitry
- Count Modes
- Data Synchronizers
- Latch
