Parameters |
Mount |
Surface Mount |
Mounting Type |
Surface Mount |
Package / Case |
16-SOIC (0.209, 5.30mm Width) |
Number of Pins |
16 |
Weight |
200.686274mg |
Operating Temperature |
-40°C~85°C TA |
Packaging |
Tape & Reel (TR) |
Series |
74AHC |
Part Status |
Obsolete |
Moisture Sensitivity Level (MSL) |
1 (Unlimited) |
Number of Terminations |
16 |
Type |
D-Type |
Subcategory |
FF/Latches |
Packing Method |
TUBE |
Technology |
CMOS |
Voltage - Supply |
2V~5.5V |
Terminal Position |
DUAL |
Terminal Form |
GULL WING |
Peak Reflow Temperature (Cel) |
NOT SPECIFIED |
Supply Voltage |
3.3V |
Time@Peak Reflow Temperature-Max (s) |
NOT SPECIFIED |
Base Part Number |
74AHC174 |
Function |
Master Reset |
Qualification Status |
Not Qualified |
Output Type |
Non-Inverted |
Number of Elements |
1 |
Polarity |
Non-Inverting |
Supply Voltage-Max (Vsup) |
5.5V |
Power Supplies |
2/5.5V |
Supply Voltage-Min (Vsup) |
2V |
Number of Circuits |
7 |
Load Capacitance |
50pF |
Output Current |
8mA |
Clock Frequency |
180MHz |
Propagation Delay |
14.5 ns |
Turn On Delay Time |
1 ns |
Family |
AHC/VHC/H/U/V |
Logic Function |
D-Type, Flip-Flop |
Current - Quiescent (Iq) |
4μA |
Current - Output High, Low |
8mA 8mA |
Max I(ol) |
0.008 A |
Number of Bits per Element |
6 |
Max Propagation Delay @ V, Max CL |
9.2ns @ 5V, 50pF |
Trigger Type |
Positive Edge |
Input Capacitance |
1.7pF |
Number of Input Lines |
3 |
Clock Edge Trigger Type |
Positive Edge |
Max Frequency@Nom-Sup |
80000000Hz |
Height Seated (Max) |
2mm |
RoHS Status |
ROHS3 Compliant |
Lead Free |
Lead Free |
SN74AHC174NSR Overview
It is embeded in 16-SOIC (0.209, 5.30mm Width) case. D flip flop is embedded in the Tape & Reel (TR) package. In the configuration, Non-Invertedis used as the output. It is configured with the trigger Positive Edge. It is mounted in the way of Surface Mount. The JK flip flop operates at 2V~5.5Vvolts. A temperature of -40°C~85°C TAis used in the operation. This electronic flip flop is of type D-Type. It belongs to the 74AHCseries of FPGAs. This D flip flop should not have a frequency greater than 180MHz. D latch consists of 1 elements. As a result, it consumes 4μA quiescent current and is not affected by external forces. Currently, there are 16 terminations. The 74AHC174family includes it. It is powered by a voltage of 3.3V . A JK flip flop with a 1.7pFfarad input capacitance is used here. Devices in the AHC/VHC/H/U/Vfamily are electronic devices. It is mounted in the way of Surface Mount. 16pins are included in its design. There is a clock edge trigger type of Positive Edgeon this device. It is part of the FF/Latchesbase part number family. Vsup reaches its maximum value at 5.5V. For normal operation, the supply voltage (Vsup) should be kept above 2V. The superior flexibility of this circuit is achieved by using 7 circuits. Due to its reliability, this T flip flop is well suited for TUBE. The D latch operates on 2/5.5V volts. Its output current of 8mAallows for maximum design flexibility. Currently, there are 3 input lines present.
SN74AHC174NSR Features
Tape & Reel (TR) package
74AHC series
16 pins
2/5.5V power supplies
SN74AHC174NSR Applications
There are a lot of Texas Instruments SN74AHC174NSR Flip Flops applications.
- Computing
- Differential Individual
- Automotive
- Storage Registers
- Frequency Divider circuits
- Data Synchronizers
- Common Clocks
- Buffered Clock
- Buffer registers
- ATE