SN74ALVCH16823DL
| Parameters | |
|---|---|
| Factory Lead Time | 1 Week |
| Lifecycle Status | ACTIVE (Last Updated: 5 days ago) |
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 56-BSSOP (0.295, 7.50mm Width) |
| Number of Pins | 56 |
| Weight | 694.790113mg |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Tube |
| Series | 74ALVCH |
| JESD-609 Code | e4 |
| Pbfree Code | yes |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 56 |
| Termination | SMD/SMT |
| Type | D-Type |
| Terminal Finish | Nickel/Palladium/Gold (Ni/Pd/Au) |
| Additional Feature | WITH CLEAR AND CLOCK ENABLE |
| Subcategory | FF/Latches |
| Technology | CMOS |
| Voltage - Supply | 1.65V~3.6V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 1.8V |
| Base Part Number | 74ALVCH16823 |
| Function | Master Reset |
| Output Type | Tri-State, Non-Inverted |
| Number of Elements | 2 |
| Polarity | Non-Inverting |
| Supply Voltage-Max (Vsup) | 3.6V |
| Power Supplies | 3.3V |
| Number of Ports | 2 |
| Output Current | 24mA |
| Number of Bits | 18 |
| Clock Frequency | 150MHz |
| Propagation Delay | 3.5 ns |
| Turn On Delay Time | 1 ns |
| Family | ALVC/VCX/A |
| Logic Function | D-Type, Flip-Flop |
| Current - Quiescent (Iq) | 40μA |
| Output Characteristics | 3-STATE |
| Current - Output High, Low | 24mA 24mA |
| Number of Bits per Element | 9 |
| Max Propagation Delay @ V, Max CL | 4.5ns @ 3.3V, 30pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 4.5pF |
| Power Supply Current-Max (ICC) | 0.04mA |
| Number of Input Lines | 5 |
| Number of Output Lines | 1 |
| Count Direction | UNIDIRECTIONAL |
| Clock Edge Trigger Type | Positive Edge |
| Translation | N/A |
| Height | 2.79mm |
| Length | 18.41mm |
| Width | 7.49mm |
| Thickness | 2.59mm |
| Radiation Hardening | No |
| REACH SVHC | No SVHC |
| RoHS Status | ROHS3 Compliant |
| Lead Free | Lead Free |
SN74ALVCH16823DL Overview
56-BSSOP (0.295, 7.50mm Width)is the packaging method. D flip flop is embedded in the Tube package. In the configuration, Tri-State, Non-Invertedis used as the output. JK flip flop uses Positive Edgeas the trigger. It is mounted in the way of Surface Mount. With a supply voltage of 1.65V~3.6V volts, it operates. The operating temperature is -40°C~85°C TA. This electronic flip flop is of type D-Type. This type of FPGA is a part of the 74ALVCH series. There should be no greater frequency than 150MHzon its output. A total of 2elements are contained within it. Despite external influences, it consumes 40μAof quiescent current. In 56terminations, a transmission line is terminated with a JK flip flop that matches its characteristic impedance. The 74ALVCH16823 family contains it. The D flip flop is powered by a voltage of 1.8V . This T flip flop has a capacitance of 4.5pF farads at the input. A device of this type belongs to the family of ALVC/VCX/A. This electronic part is mounted in the way of Surface Mount. The 56pins are designed into the board. This device's clock edge trigger type is Positive Edge. This RS flip flops is a part number FF/Latches. It is designed with a number of bits of 18. It reaches 3.6Vwhen the maximum supply voltage (Vsup) is applied. It runs on 3.3Vvolts of power. A total of 2ports are embedded in the D flip flop. With a current output of 24mA , it offers maximum design flexibility. It is designed with 1 output lines. 5input lines are available for you to choose from. Additionally, there are WITH CLEAR AND CLOCK ENABLE on the electronic flip flop that can be referred to.
SN74ALVCH16823DL Features
Tube package
74ALVCH series
56 pins
18 Bits
3.3V power supplies
SN74ALVCH16823DL Applications
There are a lot of Texas Instruments SN74ALVCH16823DL Flip Flops applications.
- Pattern generators
- Buffered Clock
- Bounce elimination switch
- Latch
- Synchronous counter
- High Performance Logic for test systems
- Shift Registers
- Load Control
- Frequency Dividers
- Modulo – n – counter
