SN74AUP1G74DQER
| Parameters | |
|---|---|
| Factory Lead Time | 1 Week |
| Lifecycle Status | ACTIVE (Last Updated: 3 days ago) |
| Contact Plating | Gold |
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 8-XFDFN |
| Number of Pins | 8 |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Tape & Reel (TR) |
| Series | 74AUP |
| JESD-609 Code | e4 |
| Pbfree Code | yes |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 8 |
| ECCN Code | EAR99 |
| Type | D-Type |
| Subcategory | FF/Latches |
| Packing Method | TR |
| Technology | CMOS |
| Voltage - Supply | 0.8V~3.6V |
| Terminal Position | DUAL |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 1.2V |
| Terminal Pitch | 0.35mm |
| Base Part Number | 74AUP1G74 |
| Function | Set(Preset) and Reset |
| Output Type | Differential |
| Polarity | Non-Inverting |
| Supply Voltage-Max (Vsup) | 3.6V |
| Number of Circuits | 1 |
| Load Capacitance | 30pF |
| Output Current | 4mA |
| Number of Bits | 1 |
| Clock Frequency | 100MHz |
| Propagation Delay | 27 ns |
| Quiescent Current | 500nA |
| Turn On Delay Time | 4 ns |
| Family | AUP/ULP/V |
| Logic Function | AND, D-Type |
| Output Characteristics | 3-STATE |
| Current - Output High, Low | 4mA 4mA |
| Max I(ol) | 0.004 A |
| Max Propagation Delay @ V, Max CL | 7ns @ 3.3V, 30pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 1.5pF |
| Power Supply Current-Max (ICC) | 0.0009mA |
| Clock Edge Trigger Type | Positive Edge |
| Max Frequency@Nom-Sup | 40000000Hz |
| Height | 400μm |
| Length | 1.4mm |
| Width | 1mm |
| Thickness | 370μm |
| Radiation Hardening | No |
| REACH SVHC | No SVHC |
| RoHS Status | ROHS3 Compliant |
| Lead Free | Lead Free |
SN74AUP1G74DQER Overview
8-XFDFNis the way it is packaged. A package named Tape & Reel (TR)includes it. Differentialis the output configured for it. It is configured with a trigger that uses a value of Positive Edge. Surface Mountis positioned in the way of this electronic part. The JK flip flop operates with an input voltage of 0.8V~3.6V volts. A temperature of -40°C~85°C TAis used in the operation. This logic flip flop is classified as type D-Type. FPGAs belonging to the 74AUPseries contain this type of chip. You should not exceed 100MHzin the output frequency of the device. There are 8 terminations, which are the practice of ending a transmission line with a device that matches the characteristic impedance of the line. It is a member of the 74AUP1G74 family. Power is supplied from a voltage of 1.2V volts. There is 1.5pF input capacitance for this T flip flop. An electronic device belonging to the family AUP/ULP/Vcan be found here. Surface Mount mounts this electronic component. 8pins are included in its design. Edge triggering is a type of triggering that allows a circuit to become active at the positive edge or the negative edge of the clock signal. The clock edge trigger type of this device is Positive Edge. The part is included in FF/Latches. It is designed with 1bits. The maximal supply voltage (Vsup) reaches 3.6V. The superior flexibility is achieved through the use of 1 circuits. As a result of its reliable performance, this T flip flop is suitable for TR. In addition to its maximum design flexibility, the output current of the T flip flop is 4mA. Quiescent current is consumed by the D latch in the amount of 500nA.
SN74AUP1G74DQER Features
Tape & Reel (TR) package
74AUP series
8 pins
1 Bits
SN74AUP1G74DQER Applications
There are a lot of Texas Instruments SN74AUP1G74DQER Flip Flops applications.
- 2 – Bit synchronous counter
- Cold spare funcion
- Buffered Clock
- Instrumentation
- Latch-up performance
- Differential Individual
- Synchronous counter
- Shift registers
- Common Clocks
- Frequency division
