SN74AUP1G74YFPR
| Parameters | |
|---|---|
| Factory Lead Time | 1 Week |
| Lifecycle Status | ACTIVE (Last Updated: 5 days ago) |
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 8-XFBGA, DSBGA |
| Number of Pins | 8 |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Tape & Reel (TR) |
| Series | 74AUP |
| JESD-609 Code | e1 |
| Pbfree Code | yes |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 8 |
| ECCN Code | EAR99 |
| Type | D-Type |
| Terminal Finish | Tin/Silver/Copper (Sn/Ag/Cu) |
| Subcategory | FF/Latches |
| Packing Method | TR |
| Technology | CMOS |
| Voltage - Supply | 0.8V~3.6V |
| Terminal Position | BOTTOM |
| Terminal Form | BALL |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 1.2V |
| Terminal Pitch | 0.4mm |
| Base Part Number | 74AUP1G74 |
| Function | Set(Preset) and Reset |
| Output Type | Differential |
| Polarity | Non-Inverting |
| Supply Voltage-Max (Vsup) | 3.6V |
| Number of Circuits | 1 |
| Load Capacitance | 30pF |
| Number of Bits | 1 |
| Clock Frequency | 100MHz |
| Propagation Delay | 5 ns |
| Quiescent Current | 500nA |
| Turn On Delay Time | 4 ns |
| Family | AUP/ULP/V |
| Logic Function | AND, D-Type, Flip-Flop |
| Output Characteristics | 3-STATE |
| Current - Output High, Low | 4mA 4mA |
| Max I(ol) | 0.004 A |
| Max Propagation Delay @ V, Max CL | 7ns @ 3.3V, 30pF |
| Prop. Delay@Nom-Sup | 27 ns |
| Trigger Type | Positive Edge |
| Input Capacitance | 1.5pF |
| Power Supply Current-Max (ICC) | 0.0009mA |
| Clock Edge Trigger Type | Positive Edge |
| Max Frequency@Nom-Sup | 40000000Hz |
| Height | 500μm |
| Length | 0m |
| Width | 0m |
| Thickness | 0m |
| Radiation Hardening | No |
| RoHS Status | ROHS3 Compliant |
| Lead Free | Lead Free |
SN74AUP1G74YFPR Overview
8-XFBGA, DSBGAis the way it is packaged. A package named Tape & Reel (TR)includes it. Differentialis the output configured for it. It is configured with the trigger Positive Edge. Surface Mountis in the way of this electric part. The JK flip flop operates with an input voltage of 0.8V~3.6V volts. A temperature of -40°C~85°C TAis considered to be the operating temperature. The type of this D latch is D-Type. The 74AUPseries comprises this type of FPGA. There should be no greater frequency than 100MHzon its output. The number of terminations is 8. D latch belongs to the 74AUP1G74 family. A voltage of 1.2V is used to power it. A JK flip flop with a 1.5pFfarad input capacitance is used here. AUP/ULP/Vis the family of this D flip flop. A part of the electronic system is mounted in the way of Surface Mount. As you can see from the design, it has pins with 8. The clock edge trigger type for this device is Positive Edge. This part is included in FF/Latches. It is designed with 1bits. Vsup reaches 3.6V, the maximal supply voltage. Despite its superior flexibility, it relies on 1 circuits to achieve it. Compared to other similar T flip flops, this device offers reliable performance and is well suited for TR. In terms of quiescent current, it consumes 500nA .
SN74AUP1G74YFPR Features
Tape & Reel (TR) package
74AUP series
8 pins
1 Bits
SN74AUP1G74YFPR Applications
There are a lot of Texas Instruments SN74AUP1G74YFPR Flip Flops applications.
- Data storage
- Storage registers
- Digital electronics systems
- Shift Registers
- Computers
- Storage Registers
- ESCC
- Communications
- Consumer
- Single Up Count-Control Line
