SN74AUP2G80YFPR
| Parameters | |
|---|---|
| Lead Free | Lead Free |
| Factory Lead Time | 1 Week |
| Lifecycle Status | ACTIVE (Last Updated: 4 days ago) |
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 8-XFBGA, DSBGA |
| Number of Pins | 8 |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Tape & Reel (TR) |
| Series | 74AUP |
| JESD-609 Code | e1 |
| Pbfree Code | yes |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 8 |
| ECCN Code | EAR99 |
| Type | D-Type |
| Terminal Finish | Tin/Silver/Copper (Sn/Ag/Cu) |
| Subcategory | FF/Latches |
| Packing Method | TR |
| Technology | CMOS |
| Voltage - Supply | 0.8V~3.6V |
| Terminal Position | BOTTOM |
| Terminal Form | BALL |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 1.2V |
| Terminal Pitch | 0.4mm |
| Time@Peak Reflow Temperature-Max (s) | NOT SPECIFIED |
| Base Part Number | 74AUP2G80 |
| Function | Standard |
| Qualification Status | Not Qualified |
| Output Type | Inverted |
| Polarity | Inverting |
| Supply Voltage-Max (Vsup) | 3.6V |
| Load Capacitance | 30pF |
| Clock Frequency | 257MHz |
| Propagation Delay | 4.3 ns |
| Turn On Delay Time | 3.1 ns |
| Family | AUP/ULP/V |
| Current - Quiescent (Iq) | 500nA |
| Current - Output High, Low | 4mA 4mA |
| Max I(ol) | 0.004 A |
| Number of Gates | 2 |
| Number of Bits per Element | 1 |
| Max Propagation Delay @ V, Max CL | 6.4ns @ 3.3V, 30pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 1.5pF |
| Power Supply Current-Max (ICC) | 0.0009mA |
| Clock Edge Trigger Type | Positive Edge |
| Height | 500μm |
| Length | 0m |
| Width | 0m |
| Thickness | 0m |
| RoHS Status | ROHS3 Compliant |
SN74AUP2G80YFPR Overview
As a result, it is packaged as 8-XFBGA, DSBGA. Package Tape & Reel (TR)embeds it. Currently, the output is configured to use Inverted. In the configuration of the trigger, Positive Edgeis used. Surface Mountmounts this electrical part. The JK flip flop operates with an input voltage of 0.8V~3.6V volts. It is operating at a temperature of -40°C~85°C TA. This D latch has the type D-Type. In this case, it is a type of FPGA belonging to the 74AUP series. There should be no greater frequency than 257MHzon its output. There is a consumption of 500nAof quiescent energy. A total of 8 terminations have been made. It is a member of the 74AUP2G80 family. It is powered by a voltage of 1.2V . This T flip flop has a capacitance of 1.5pF farads at the input. In terms of electronic devices, this device belongs to the AUP/ULP/Vfamily of devices. There is an electronic part that is mounted in the way of Surface Mount. As you can see from the design, it has pins with 8. Its clock edge trigger type is Positive Edge. It is included in FF/Latches. In this case, the maximum supply voltage (Vsup) reaches 3.6V. A reliable performance of this D flip flop makes it well suited for use in TR. This building block contains 2 gates as its basic building block.
SN74AUP2G80YFPR Features
Tape & Reel (TR) package
74AUP series
8 pins
2 gates
SN74AUP2G80YFPR Applications
There are a lot of Texas Instruments SN74AUP2G80YFPR Flip Flops applications.
- Instrumentation
- Buffer registers
- Power down protection
- Load Control
- Frequency Divider circuits
- Registers
- Buffered Clock
- Count Modes
- Synchronous counter
- Modulo – n – counter
