SN74AVC16374ZQLR
| Parameters | |
|---|---|
| Lifecycle Status | LIFEBUY (Last Updated: 4 days ago) |
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 56-VFBGA |
| Number of Pins | 56 |
| Weight | 58.28662mg |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Tape & Reel (TR) |
| Series | 74AVC |
| JESD-609 Code | e1 |
| Pbfree Code | yes |
| Part Status | Last Time Buy |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 56 |
| ECCN Code | EAR99 |
| Type | D-Type |
| Terminal Finish | Tin/Silver/Copper (Sn/Ag/Cu) |
| Subcategory | FF/Latches |
| Packing Method | TR |
| Technology | CMOS |
| Voltage - Supply | 1.4V~3.6V |
| Terminal Position | BOTTOM |
| Terminal Form | BALL |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 1.5V |
| Terminal Pitch | 0.65mm |
| Time@Peak Reflow Temperature-Max (s) | NOT SPECIFIED |
| Base Part Number | 74AVC16374 |
| Function | Standard |
| Qualification Status | Not Qualified |
| Output Type | Tri-State, Non-Inverted |
| Number of Elements | 2 |
| Polarity | Non-Inverting |
| Supply Voltage-Max (Vsup) | 3.6V |
| Power Supplies | 3.3V |
| Supply Voltage-Min (Vsup) | 1.4V |
| Load Capacitance | 30pF |
| Number of Ports | 2 |
| Output Current | 12mA |
| Number of Bits | 16 |
| Clock Frequency | 200MHz |
| Propagation Delay | 6.7 ns |
| Turn On Delay Time | 7.3 ns |
| Family | AVC |
| Logic Function | D-Type, Flip-Flop |
| Current - Quiescent (Iq) | 40μA |
| Output Characteristics | 3-STATE |
| Current - Output High, Low | 12mA 12mA |
| Max Propagation Delay @ V, Max CL | 3.3ns @ 3.3V, 30pF |
| Prop. Delay@Nom-Sup | 3.3 ns |
| Trigger Type | Positive Edge |
| Input Capacitance | 3pF |
| Power Supply Current-Max (ICC) | 0.04mA |
| Number of Output Lines | 8 |
| Count Direction | UNIDIRECTIONAL |
| Clock Edge Trigger Type | Positive Edge |
| Translation | N/A |
| Height | 1mm |
| Length | 7mm |
| Width | 4.5mm |
| Thickness | 750μm |
| RoHS Status | ROHS3 Compliant |
| Lead Free | Lead Free |
SN74AVC16374ZQLR Overview
In the form of 56-VFBGA, it has been packaged. D flip flop is embedded in the Tape & Reel (TR) package. T flip flop is configured with an output of Tri-State, Non-Inverted. There is a trigger configured with Positive Edge. There is an electronic component mounted in the way of Surface Mount. The JK flip flop operates with an input voltage of 1.4V~3.6V volts. The operating temperature is -40°C~85°C TA. D-Typeis the type of this D latch. In terms of FPGAs, it belongs to the 74AVC series. It should not exceed 200MHzin its output frequency. D latch consists of 2 elements. It consumes 40μA of quiescent Terminations are 56. The 74AVC16374 family contains this object. A voltage of 1.5V is used as the power supply for this D latch. Input capacitance of this device is 3pF farads. In terms of electronic devices, this device belongs to the AVCfamily of devices. It is mounted by the way of Surface Mount. There are 56pins on it. In this device, the clock edge trigger type is Positive Edge. It is part of the FF/Latchesbase part number family. The flip flop is designed with 16bits. As soon as 3.6Vis reached, Vsup reaches its maximum value. Normally, the supply voltage (Vsup) should be above 1.4V. This D flip flop is well suited for TR based on its reliable performance. The D latch operates on 3.3V volts. The D flip flop is embedded with 2ports. With an output current of 12mA, this device offers maximum design flexibility. It is designed with 8 output lines.
SN74AVC16374ZQLR Features
Tape & Reel (TR) package
74AVC series
56 pins
16 Bits
3.3V power supplies
SN74AVC16374ZQLR Applications
There are a lot of Texas Instruments SN74AVC16374ZQLR Flip Flops applications.
- Dynamic threshold performance
- Count Modes
- Data storage
- Set-reset capability
- QML qualified product
- Computing
- Matched Rise and Fall
- Latch
- Computers
- Balanced Propagation Delays
