SN74F112N
| Parameters | |
|---|---|
| Factory Lead Time | 1 Week |
| Lifecycle Status | ACTIVE (Last Updated: 3 days ago) |
| Mount | Through Hole |
| Mounting Type | Through Hole |
| Package / Case | 16-DIP (0.300, 7.62mm) |
| Number of Pins | 16 |
| Weight | 951.693491mg |
| Operating Temperature | 0°C~70°C TA |
| Packaging | Tube |
| Series | 74F |
| JESD-609 Code | e4 |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 16 |
| ECCN Code | EAR99 |
| Type | JK Type |
| Terminal Finish | Nickel/Palladium/Gold (Ni/Pd/Au) |
| Subcategory | FF/Latches |
| Technology | TTL |
| Voltage - Supply | 4.5V~5.5V |
| Terminal Position | DUAL |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 5V |
| Time@Peak Reflow Temperature-Max (s) | NOT SPECIFIED |
| Base Part Number | 74F112 |
| Function | Set(Preset) and Reset |
| Qualification Status | Not Qualified |
| Output Type | Differential |
| Operating Supply Voltage | 5V |
| Polarity | Non-Inverting |
| Power Supplies | 5V |
| Number of Circuits | 2 |
| Load Capacitance | 50pF |
| Output Current | 20mA |
| Clock Frequency | 130MHz |
| Propagation Delay | 4.6 ns |
| Turn On Delay Time | 4.6 ns |
| Family | F/FAST |
| Logic Function | AND, Flip-Flop, JK-Type |
| Current - Quiescent (Iq) | 19mA |
| Current - Output High, Low | 1mA 20mA |
| Number of Bits per Element | 1 |
| Max Propagation Delay @ V, Max CL | 6.5ns @ 5V, 50pF |
| Prop. Delay@Nom-Sup | 7.5 ns |
| Trigger Type | Negative Edge |
| Schmitt Trigger | No |
| Clock Edge Trigger Type | Negative Edge |
| Height | 5.08mm |
| Length | 19.3mm |
| Width | 6.35mm |
| Thickness | 3.9mm |
| REACH SVHC | No SVHC |
| RoHS Status | ROHS3 Compliant |
| Lead Free | Lead Free |
SN74F112N Overview
16-DIP (0.300, 7.62mm)is the way it is packaged. D flip flop is embedded in the Tube package. In the configuration, Differentialis used as the output. This trigger uses the value Negative Edge. Through Holeis in the way of this electric part. A 4.5V~5.5Vsupply voltage is required for it to operate. In the operating environment, the temperature is 0°C~70°C TA. JK Typedescribes this flip flop. The FPGA belongs to the 74F series. There should be no greater frequency than 130MHzon its output. It consumes 19mA of quiescent current without being affected by external factors. Currently, there are 16 terminations. D latch belongs to the 74F112 family. It is powered by a voltage of 5V . F/FASTis the family of this D flip flop. There is an electronic part that is mounted in the way of Through Hole. The electronic flip flop is designed with pins 16. This device exhibits a clock edge trigger type of Negative Edge. There is a FF/Latchesbase part number assigned to the RS flip flops. Its superior flexibility is attributed to its use of 2 circuits. It runs on 5Vvolts of power. In order to achieve high efficiency, the supply voltage should be maintained at 5V. The 20mA output current allows it to be designed with the greatest amount of flexibility.
SN74F112N Features
Tube package
74F series
16 pins
5V power supplies
SN74F112N Applications
There are a lot of Texas Instruments SN74F112N Flip Flops applications.
- Guaranteed simultaneous switching noise level
- Buffered Clock
- Single Down Count-Control Line
- Buffer registers
- Digital electronics systems
- Convert a momentary switch to a toggle switch
- Common Clocks
- Synchronous counter
- Matched Rise and Fall
- CMOS Process
