SN74LS109ANSR
| Parameters | |
|---|---|
| Factory Lead Time | 1 Week |
| Lifecycle Status | ACTIVE (Last Updated: 2 days ago) |
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 16-SOIC (0.209, 5.30mm Width) |
| Number of Pins | 16 |
| Weight | 200.686274mg |
| Operating Temperature | 0°C~70°C TA |
| Packaging | Tape & Reel (TR) |
| Series | 74LS |
| JESD-609 Code | e4 |
| Pbfree Code | yes |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 16 |
| Type | JK Type |
| Terminal Finish | Nickel/Palladium/Gold (Ni/Pd/Au) |
| Additional Feature | INVERTED K INPUT |
| Subcategory | FF/Latches |
| Packing Method | TR |
| Technology | TTL |
| Voltage - Supply | 4.75V~5.25V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 5V |
| Time@Peak Reflow Temperature-Max (s) | NOT SPECIFIED |
| Base Part Number | 74LS109 |
| Function | Set(Preset) and Reset |
| Qualification Status | Not Qualified |
| Output Type | Differential |
| Operating Supply Voltage | 5V |
| Polarity | Non-Inverting |
| Power Supplies | 5V |
| Number of Circuits | 2 |
| Output Current | 8mA |
| Clock Frequency | 33MHz |
| Propagation Delay | 40 ns |
| Turn On Delay Time | 13 ns |
| Family | LS |
| Logic Function | AND, Flip-Flop, JK-Type |
| Current - Output High, Low | 400μA 8mA |
| Max I(ol) | 0.008 A |
| Number of Bits per Element | 1 |
| Max Propagation Delay @ V, Max CL | 25ns @ 5V, 15pF |
| Trigger Type | Positive Edge |
| Schmitt Trigger | No |
| Number of Input Lines | 5 |
| Clock Edge Trigger Type | Positive Edge |
| Height | 2mm |
| Length | 10.3mm |
| Width | 5.3mm |
| Thickness | 1.95mm |
| RoHS Status | ROHS3 Compliant |
| Lead Free | Lead Free |
SN74LS109ANSR Overview
16-SOIC (0.209, 5.30mm Width)is the packaging method. It is included in the package Tape & Reel (TR). T flip flop uses Differentialas the output. The trigger it is configured with uses Positive Edge. Surface Mountis in the way of this electric part. Powered by a 4.75V~5.25Vvolt supply, it operates as follows. A temperature of 0°C~70°C TAis used in the operation. JK Typeis the type of this D latch. In this case, it is a type of FPGA belonging to the 74LS series. There should be no greater frequency than 33MHzon its output. In 16terminations, a transmission line is terminated with a JK flip flop that matches its characteristic impedance. Members of the 74LS109family make up this object. An input voltage of 5Vpowers the D latch. In this case, the D flip flop belongs to the LSfamily. There is an electronic component mounted in the way of Surface Mount. Basically, it is designed with a set of 16 pins. This device has the clock edge trigger type of Positive Edge. The RS flip flops belongs to FF/Latches base part number. The superior flexibility is achieved through the use of 2 circuits. In light of its reliable performance, this T flip flop is well suited for TR. A power supply of 5Vis required to operate it. In order to ensure high efficiency, the supply voltage should remain at 5V. The output current of 8mA makes it feature maximum design flexibility. This input has 5lines in it. Additionally, you may refer to the D latch's additional INVERTED K INPUT.
SN74LS109ANSR Features
Tape & Reel (TR) package
74LS series
16 pins
5V power supplies
SN74LS109ANSR Applications
There are a lot of Texas Instruments SN74LS109ANSR Flip Flops applications.
- Counters
- Frequency Dividers
- Test & Measurement
- Memory
- Individual Asynchronous Resets
- Instrumentation
- Parallel data storage
- Latch
- Computers
- Computing
