SN74LV74AMPWREP
| Parameters | |
|---|---|
| Factory Lead Time | 1 Week |
| Lifecycle Status | ACTIVE (Last Updated: 3 days ago) |
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 14-TSSOP (0.173, 4.40mm Width) |
| Number of Pins | 14 |
| Weight | 57.209338mg |
| Operating Temperature | -55°C~125°C TA |
| Packaging | Tape & Reel (TR) |
| Series | 74LV |
| JESD-609 Code | e4 |
| Pbfree Code | yes |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 14 |
| ECCN Code | EAR99 |
| Type | D-Type |
| Terminal Finish | Nickel/Palladium/Gold (Ni/Pd/Au) |
| Subcategory | FF/Latches |
| Packing Method | TR |
| Technology | CMOS |
| Voltage - Supply | 2V~5.5V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 2.5V |
| Time@Peak Reflow Temperature-Max (s) | NOT SPECIFIED |
| Base Part Number | 74LV74 |
| Function | Set(Preset) and Reset |
| Qualification Status | Not Qualified |
| Output Type | Differential |
| Polarity | Non-Inverting |
| Supply Voltage-Max (Vsup) | 5.5V |
| Power Supplies | 3.3V |
| Supply Voltage-Min (Vsup) | 2V |
| Number of Circuits | 2 |
| Load Capacitance | 50pF |
| Output Current | 12mA |
| Clock Frequency | 140MHz |
| Propagation Delay | 20 ns |
| Turn On Delay Time | 9.8 ns |
| Family | LV/LV-A/LVX/H |
| Logic Function | AND, D-Type |
| Current - Quiescent (Iq) | 20μA |
| Current - Output High, Low | 12mA 12mA |
| Number of Bits per Element | 1 |
| Max Propagation Delay @ V, Max CL | 9.9ns @ 5V, 50pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 2pF |
| Number of Output Lines | 1 |
| fmax-Min | 75 MHz |
| Clock Edge Trigger Type | Positive Edge |
| Max Frequency@Nom-Sup | 45000000Hz |
| Height | 1.2mm |
| Length | 5mm |
| Width | 4.4mm |
| Thickness | 1mm |
| RoHS Status | ROHS3 Compliant |
| Lead Free | Lead Free |
SN74LV74AMPWREP Overview
It is embeded in 14-TSSOP (0.173, 4.40mm Width) case. As part of the package Tape & Reel (TR), it is embedded. This output is configured with Differential. JK flip flop uses Positive Edgeas the trigger. This electronic part is mounted in the way of Surface Mount. The supply voltage is set to 2V~5.5V. Temperature is set to -55°C~125°C TA. The type of this D latch is D-Type. JK flip flop is a part of the 74LVseries of FPGAs. There should be no greater frequency than 140MHzon its output. It consumes 20μA of quiescent current without being affected by external factors. 14terminations have occurred. The object belongs to the 74LV74 family. Power is provided by a 2.5V supply. JK flip flop input capacitance is 2pF farads. The electronic device belongs to the LV/LV-A/LVX/Hfamily. There is an electronic part mounted in the way of Surface Mount. With its 14pins, it is designed to work with most electronic flip flops. It has a clock edge trigger type of Positive Edge. This RS flip flops is a part number FF/Latches. As soon as 5.5Vis reached, Vsup reaches its maximum value. For normal operation, the supply voltage (Vsup) should be kept above 2V. Its superior flexibility is attributed to its use of 2 circuits. Considering the reliability of this T flip flop, it is well suited for TR. There are 3.3V power supplies attached to it. Its output current of 12mAallows for maximum design flexibility. It operates with 1 output lines.
SN74LV74AMPWREP Features
Tape & Reel (TR) package
74LV series
14 pins
3.3V power supplies
SN74LV74AMPWREP Applications
There are a lot of Texas Instruments SN74LV74AMPWREP Flip Flops applications.
- Latch
- ESCC
- Reduced system switching noise
- Frequency Divider circuits
- Bounce elimination switch
- Buffer registers
- Memory
- Common Clocks
- Asynchronous counter
- Storage Registers
