SN74LV74APWE4
| Parameters | |
|---|---|
| Mounting Type | Surface Mount |
| Package / Case | 14-TSSOP (0.173, 4.40mm Width) |
| Supplier Device Package | 14-TSSOP |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Tube |
| Series | 74LV |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Type | D-Type |
| Voltage - Supply | 2V~5.5V |
| Function | Set(Preset) and Reset |
| Output Type | Differential |
| Number of Elements | 2 |
| Clock Frequency | 140MHz |
| Current - Quiescent (Iq) | 20μA |
| Current - Output High, Low | 12mA 12mA |
| Number of Bits per Element | 1 |
| Max Propagation Delay @ V, Max CL | 9.3ns @ 5V, 50pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 2pF |
| RoHS Status | ROHS3 Compliant |
SN74LV74APWE4 Overview
The flip flop is packaged in 14-TSSOP (0.173, 4.40mm Width). The Tubepackage contains it. The output it is configured with uses Differential. It is configured with a trigger that uses Positive Edge. There is an electric part mounted in the way of Surface Mount. The JK flip flop operates with an input voltage of 2V~5.5V volts. It is operating at a temperature of -40°C~85°C TA. D-Typeis the type of this D latch. This type of FPGA is a part of the 74LV series. Its output frequency should not exceed 140MHz. The element count is 2 . There is 20μA quiescent consumption. The input capacitance of this T flip flop is 2pF farads, which is defined as the capacitance between the input terminals of an op amp with either input grounded.
SN74LV74APWE4 Features
Tube package
74LV series
SN74LV74APWE4 Applications
There are a lot of Rochester Electronics, LLC SN74LV74APWE4 Flip Flops applications.
- Dynamic threshold performance
- Data storage
- Individual Asynchronous Resets
- Storage registers
- Shift registers
- 2 – Bit synchronous counter
- Clock pulse
- Bus hold
- Cold spare funcion
- Control circuits
